Alternate Vertical CMOS Channels for Smaller Inverter Footprints
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Solution Overview
Problem
The challenge of scaling down the footprint of CMOS inverters is significant due to the difficulty in reducing the size of transistors formed on the same level height on a wafer.
Innovation Solution
A new inverter structure is developed with PFET and NFET channels alternately arranged vertically, utilizing sacrificial layers and selective etching processes to form nanosheets, nanowires, or nanorings that serve as channel layers, allowing for reduced footprint and balanced current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If transistors are formed on the same level height on a wafer, then conventional fabrication processes can be used, but the footprint of CMOS inverters cannot be scaled down effectively
Solution Approach 1:
The patent transitions from planar transistor arrangement to vertical stacking, forming NFET and PFET channels at different height levels. Multiple channel layers (first, second, third channel layers) are stacked vertically with gate structures between them, enabling three-dimensional integration. This vertical arrangement dramatically reduces the horizontal footprint of the inverter while maintaining functional transistor structures with source, drain, and gate regions.
2Area of stationary object
If vertical stacking of NFET and PFET channels is implemented, then footprint is reduced, but selective etching and fabrication precision requirements increase
Solution Approach 1:
The patent employs selective etching processes that target specific material compositions at different locations. Sacrificial layers with distinct material properties (e.g., different etch rates or chemical compositions) are used between channel layers. The etching process is localized to remove only the sacrificial layers, creating vertical separation between NFET and PFET channels while preserving the channel structures themselves. This local selectivity enables precise vertical patterning.
Solution Approach 2:
Sacrificial layers serve as intermediary structures during fabrication. These temporary layers are positioned between the NFET and PFET channel layers and are removed selectively through etching. The sacrificial layers mediate the formation of vertical channels by providing a removable template that defines the separation between n-type and p-type regions, enabling the complex vertical structure to be built step-by-step.
3Reliability
If alternate complementary channels are vertically arranged, then current balance is improved, but fabrication process complexity increases
Solution Approach 1:
The inverter is segmented into distinct vertical sections: NFET channel regions, PFET channel regions, and gate structures between them. Each transistor type is separated into its own vertical zone with dedicated source, drain, and channel regions. This segmentation allows independent optimization of NFET and PFET characteristics while maintaining overall current balance through controlled geometry and material composition of each segment.
Solution Approach 2:
The patent uses composite material structures with different semiconductor materials for NFET and PFET channels (e.g., different bandgap materials or doping configurations). These composite structures enable tailored electrical properties for each transistor type, allowing current balance to be achieved through material selection rather than purely geometric adjustments, thus managing fabrication complexity.
Data Source
AI summary
A device comprises a gate structure, n-type source/drain features, p-type source/drain features, an NFET channel, and a PFET channel. The gate structure is over a substrate. The n-type source/drain features are on opposite first and second sides of the gate structure, respectively. The p-type source/drain features are on opposite third and fourth sides of the gate structure, respectively. The NFET channel extends within the gate structure and connects the n-type source/drain features. The PFET channel extends within the gate structure and connects the p-type source/drain features. The NFET channel and the PFET channel are vertically spaced apart by the gate structure.