Vertical Complementary Transistor Layout for Smaller CMOS Footprints
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Solution Overview
Problem
Conventional complementary metal-oxide-semiconductor field effect transistors (CMOSFETs) face challenges with larger footprints due to coplanar designs and lagging hole mobilities compared to electron mobilities, especially as device dimensions shrink for advanced technology nodes.
Innovation Solution
The development of vertically-oriented hybrid CMOSFETs, comprising a bottom p-type FinFET and a top n-type MBC transistor, or vice versa, with vertically aligned source and drain features, allowing for conductive coupling and integration of backside source contacts and power rails to enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If coplanar CMOSFET design is used, then device integration is simplified, but footprint area increases
Solution Approach 1:
The patent transitions from coplanar (2D) transistor arrangement to vertically stacked (3D) configuration, where n-type and p-type transistors are stacked one above the other sharing common source/drain regions. This dimensional change reduces footprint area while maintaining integration simplicity through the shared structural elements.
2Ease of manufacture
If conventional planar structure is used, then manufacturing process is simpler, but gate control over channel is insufficient
Solution Approach 1:
The gate structure extends vertically in the third dimension, wrapping around the channel region from multiple sides (front, back, and sidewalls). This 3D gate configuration provides superior electrostatic control over the channel compared to planar gates, improving device reliability while remaining compatible with standard semiconductor fabrication processes.
Solution Approach 2:
The gate structure is nested around the channel region, with the gate dielectric and gate electrode forming concentric layers that completely surround the channel. This nested configuration maximizes gate-to-channel coupling and control effectiveness.
3Productivity
If device dimensions are scaled down for advanced nodes, then production efficiency increases, but hole mobility lag worsens
Solution Approach 1:
The vertically stacked architecture with multi-sided gate control creates enhanced electric field distribution that compensates for mobility differences between hole and electron transport. The 3D gate structure provides stronger control over the channel, improving hole mobility in p-type transistors to reduce the mobility lag relative to n-type transistors.
Data Source
AI summary
A semiconductor device according to the present disclosure includes a first transistor and a second transistor disposed over the first transistor. The first transistor includes a plurality of channel members vertically stacked over one another, and a first source/drain feature adjoining the plurality of channel members. The second transistor includes a fin structure, and a second source/drain feature adjoining the fin structure. The semiconductor device further includes a conductive feature electrically connecting the first source/drain feature and the second source/drain feature.