Vertical CMOS Inverter With Hybrid Gate for Higher Memory Density
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Solution Overview
Problem
Microelectronic device designers face challenges in increasing the integration density and reducing fabrication costs while maintaining performance, particularly in memory device design, due to limitations in scaling and storage density.
Innovation Solution
The design incorporates a vertically oriented CMOS inverter with a hybrid gate electrode shared by NMOS and PMOS transistors, featuring regions with different material compositions to optimize threshold voltage characteristics and electrical coupling, which improves scaling and reduces manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional planar CMOS inverter design is used, then fabrication process is simpler, but integration density is lower and short channel effects are more severe
Solution Approach 1:
The patent transitions from planar (2D) gate geometry to vertically stacked 3D gate structure. The gate electrode extends in the vertical direction through the channel, creating a three-dimensional configuration that increases the effective gate area and improves control over the channel, thereby increasing integration density while maintaining fabrication feasibility through adapted processes.
Solution Approach 2:
The gate electrode is positioned within and surrounds the channel structure in a nested configuration. The gate wraps around the channel from multiple directions in the vertical stack, creating a nested geometry that maximizes the gate's control over the channel while minimizing the lateral footprint, thus improving integration density.
2Manufacturing precision
If feature dimensions are reduced to increase density, then integration density improves, but short channel effects worsen
Solution Approach 1:
By extending the gate into the vertical dimension, the effective gate length is increased without increasing the lateral dimensions. This 3D configuration provides better electrostatic control over the channel, suppressing short channel effects even as lateral feature sizes are reduced to increase integration density.
Solution Approach 2:
The gate electrode employs a hybrid structure with different material compositions in different regions (first region with first material, second region with second material). This composite gate structure allows optimization of electrical characteristics to improve channel control and reduce short channel effects while maintaining scaled dimensions.
3Reliability
If separate gate electrodes are used for NMOS and PMOS transistors, then each transistor can be optimized, but device complexity and fabrication difficulty increase
Solution Approach 1:
The patent combines the gate electrodes of the NMOS and PMOS transistors into a single shared gate electrode structure. This merged gate extends vertically and controls both transistors, reducing the total number of gate structures needed while maintaining the ability to independently optimize transistor performance through regional material composition variations within the unified gate.
Solution Approach 2:
The single gate electrode structure serves multiple functions by simultaneously controlling both the NMOS and PMOS transistors. This universal gate structure reduces device complexity while the hybrid material composition allows it to perform the specialized functions of controlling both transistor types effectively.
4Manufacturing precision
If vertically stacked transistor configuration is used, then integration density increases, but fabrication complexity increases
Solution Approach 1:
The vertically stacked configuration utilizes the vertical dimension to increase integration density by stacking transistors and gate structures above each other rather than placing them side-by-side in the lateral plane. This 3D arrangement achieves higher density while the gate's vertical extension naturally accommodates this stacking geometry.
Solution Approach 2:
By merging the gate electrodes into a single shared structure that extends vertically through both transistors, the patent reduces the number of separate fabrication steps needed compared to creating separate gates for each vertically stacked transistor. This unified gate structure simplifies the fabrication process while maintaining the benefits of vertical stacking for increased integration density.
Data Source
AI summary
An inverter includes a transistor, an additional transistor overlying the transistor, and a hybrid gate electrode interposed between and shared by the transistor and the additional transistor. The hybrid gate electrode includes a region overlying a channel structure of the transistor, an additional region overlying the region and underlying an additional channel structure of the additional transistor, and further region interposed between the region and the additional region. The region has a first material composition. The additional region has a second material composition different than the first material composition of the region. Memory devices and electronic systems are also described.