Vertical CMOS Inverter Pillar Scaling
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Solution Overview
Problem
Current semiconductor manufacturing technologies face limitations in reducing circuit size and adjusting current drive in integrated circuits, such as inverter circuits, which restricts further scaling and density enhancement.
Innovation Solution
A CMOS inverter structure employing vertical transistor structures with epitaxially grown semiconductor pillars and a gate dielectric layer, allowing for easier scaling and adjustment of current drive through selective epitaxial growth and lithography-defined channel width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If traditional two-dimensional integrated circuit design is used, then manufacturing process is well-established, but circuit size reduction and density enhancement are limited
Solution Approach 1:
The patent transitions from traditional two-dimensional planar transistors to three-dimensional vertical transistors. The channel is formed vertically through the substrate thickness rather than laterally in the plane, enabling continued scaling as circuit density increases. This dimensional transition allows the channel length to be defined by thin film deposition thickness rather than photolithography, providing better control at smaller scales.
Solution Approach 2:
The patent changes the fundamental geometric parameters of the transistor structure from planar to vertical orientation. By defining channel length through film thickness parameters rather than lithographic patterning, the design enables scaling to smaller dimensions while maintaining manufacturing feasibility through established thin film deposition techniques.
2Quantity of substance
If circuit size is reduced to increase density, then device density improves, but current drive adjustment capability is lost
Solution Approach 1:
The patent enables dynamic adjustment of transistor characteristics through the vertical structure design. By controlling the vertical channel dimensions and doping profiles through epitaxial growth, the current drive can be tuned to accommodate different application requirements while maintaining high device density, providing both scalability and adaptability.
3Manufacturing precision
If photolithography is used to define channel length, then manufacturing is straightforward, but dimension control and scaling precision are insufficient
Solution Approach 1:
The patent replaces the mechanical photolithography patterning process with a thin film deposition-based approach for defining channel length. The channel length is determined by the thickness of deposited semiconductor layers rather than by optical patterning, providing superior dimension control and scaling precision while using well-established semiconductor fabrication techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables compact and versatile CMOS inverters with improved dimension control and simpler layout requirements, facilitating easier scaling and fine-tuning of current drive compared to traditional FinFET technologies.
Implementation Method 1
a gate dielectric layer surrounding the semiconductor pillar structure
Implementation Method 2
The semiconductor pillar structure can be an epitaxially grown semiconductor material, which can have a substantially monocrystalline structure
Data Source
AI summary
A method for manufacturing an inverter circuit includes providing a semiconductor substrate and forming at least one dielectric trench isolation structure in the semiconductor substrate to divide the semiconductor substrate into first and second regions. A P+ doped portion and an N+ doped portion is formed in each of the first and second regions. Gate structure layers are then deposited over the semiconductor substrate. A first opening is formed in the gate structure layers over the P+ doped portion of a first region and a second opening is formed in the gate structure layers over the N+ doped portion of a second region. A gate dielectric layer is then formed on an inner side of the first and second openings. The surface of the semiconductor substrate in the first and second openings is etched. A semiconductor material is formed in the first and second openings by selective epitaxial growth.