Vertical Coaxial Resonators for Quantum Chip Noise Shielding
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Solution Overview
Problem
Quantum computing architectures face challenges in maintaining coherence due to noise from the environment, particularly charge noise, which causes decoherence and disrupts the functioning of qubits, and the two-dimensional layout makes it difficult to implement processing and input/output architectures in limited space.
Innovation Solution
The use of vertical coaxial resonators with a superconducting center conductor and a coaxial dielectric layer, positioned outside the plane of the qubits, reduces interference and noise, while the grounded conductive carrier body further shields the qubits from environmental noise, allowing for high-Q readout and suppression of coupling with quantum buses and the environment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional layout is used for quantum computing architecture, then ease of manufacture is improved, but area utilization deteriorates due to limited space for processing and input/output architecture
Solution Approach 1:
The patent transitions from a two-dimensional planar layout to a three-dimensional vertical architecture by positioning readout resonators perpendicular to the quantum chip plane. This dimensional change allows resonators to extend through the substrate, enabling simultaneous access to multiple qubits without increasing the chip's footprint area, thus resolving the contradiction between ease of manufacture and area utilization.
2Device complexity
If conventional readout resonators are used, then device complexity is reduced, but coherence deteriorates due to noise from the surrounding environment causing decoherence
Solution Approach 1:
The patent introduces an intermediary grounded substrate structure that mediates between the readout resonators and the environment. This substrate acts as a shield, blocking environmental noise and interference from reaching the qubits, thereby maintaining coherence while using conventional resonator designs. The intermediary layer resolves the contradiction by adding protection without significantly increasing overall device complexity.
3Device complexity
If readout resonators are positioned in the plane of qubits, then device complexity is minimized, but area deteriorates due to interference and noise from the resonators
Solution Approach 1:
The patent positions readout resonators in the vertical dimension perpendicular to the quantum chip plane, rather than in the same plane as the qubits. This spatial separation in the third dimension eliminates interference and noise issues while maintaining minimal device complexity, as the resonators can be integrated into the substrate structure without adding lateral footprint.
4Reliability
If environmental shielding is enhanced, then coherence is improved, but device complexity increases due to additional shielding structures
Solution Approach 1:
The patent merges the shielding function with the existing substrate structure by grounding the substrate and utilizing it as both a mechanical support and an electromagnetic shield. This integration combines multiple functions into a single structure, enhancing coherence through environmental shielding without proportionally increasing device complexity, as the substrate serves dual purposes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances coherence by minimizing thermal and charge noise, allowing for longer maintenance of quantum states and efficient computation, while the out-of-plane resonators free up space for qubits and quantum buses, enabling more feasible and robust quantum computing operations.
Implementation Method 1
vertical coaxial resonators with a superconducting center conductor and a coaxial dielectric layer, positioned outside the plane of the qubits, reduces interference and noise, while the grounded conductive carrier body further shields the qubits from environmental noise
Implementation Method 2
Each readout resonator has a superconducting center conductor and a coaxial dielectric layer
Data Source
AI summary
Quantum computing devices include a chip carrier that has a conductive carrier body and one or more readout resonators in the conductive carrier body. Each readout resonator has a center conductor and a coaxial dielectric layer. A quantum chip is on the chip carrier and includes one or more qubits positioned over respective readout resonators.