Vertical Semiconductor Column Memory with Dual Gate Control
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Solution Overview
Problem
Conventional semiconductor memory devices face limitations in integration, power consumption, and operational efficiency due to increased leakage current, subthreshold swing, and the inability to flexibly switch between volatile and nonvolatile modes, especially as they are scaled down for use in handheld devices and multifunctional apparatuses.
Innovation Solution
A semiconductor memory device with a vertical semiconductor column structure, featuring a p-i-n structure and dual gate electrodes, which reduces leakage current and power consumption, and allows for selective volatile/nonvolatile operation using a low applied voltage, high on-off current ratio, and low subthreshold swing, enabling efficient data storage and retrieval in a single device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional 1T-1C structure is used for volatile memory, then basic memory function is achieved, but integration is limited and leakage current increases
Solution Approach 1:
The patent transitions from planar 1T-1C structure to a vertical columnar structure where the semiconductor column extends in the vertical dimension. This dimensional change enables higher integration density while the dual gate configuration (front gate and back gate) provides independent control to suppress leakage current through the column, resolving the contradiction between integration and leakage.
Solution Approach 2:
The semiconductor column is segmented into multiple functional regions (first conductivity type region, intrinsic region, second conductivity type region) along its length. This segmentation allows different sections to perform different functions: charge storage, transport, and control, enabling both high integration and low leakage through optimized regional characteristics.
2Reliability
If flash memory structure is used, then nonvolatile storage is achieved, but subthreshold swing is 60 mV/dec causing small sensing margin and data errors
Solution Approach 1:
The patent achieves subthreshold swing less than 60 mV/dec by utilizing the unique physics of the vertical p-i-n column structure with dual gate control. The intrinsic region acts as a depletion layer that can be fully depleted, creating a sharper transition between off and on states. This parameter change in subthreshold swing directly improves the current sensing margin while maintaining nonvolatile retention characteristics.
3Productivity
If memory devices are scaled down for high capacity, then integration increases, but short-channel effect causes performance degradation
Solution Approach 1:
By scaling vertically rather than laterally, the patent maintains effective channel length control while increasing storage capacity. The vertical column structure with top and bottom gate control eliminates short-channel effects that plague planar scaled devices, as the gate electrodes can effectively control the depletion region throughout the entire column height regardless of lateral dimensions.
4Adaptability or versatility
If conventional volatile or nonvolatile devices are used, then specific operation mode is achieved, but flexible switching between modes is not possible
Solution Approach 1:
The patent creates a universal memory cell that can operate in both volatile and nonvolatile modes using the same physical structure. By controlling the voltage applied to the front and back gates independently, the device can be configured for different operation modes without requiring separate device structures, achieving mode flexibility while maintaining relatively simple device architecture.
Data Source
AI summary
A memory device includes: a semiconductor column extending vertically on a substrate and including a source region of a first conductivity type, an intrinsic region, and a drain region of a second conductivity type; a first gate electrode disposed adjacent to the drain region to cover the intrinsic region; a second gate electrode spaced apart from the first gate electrode and disposed adjacent to the source region to cover the intrinsic region; a first gate insulating layer disposed between the first gate electrode and the intrinsic region; and a second gate insulating layer disposed between the second gate electrode and the intrinsic region.