Vertical Common Source Line in 3D NAND Memory
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Solution Overview
Problem
Current semiconductor devices with three-dimensional memory structures face challenges in efficiently forming cell strings with a common source line, which affects capacitance and electric characteristics.
Innovation Solution
The semiconductor device includes first and second cell strings arranged in parallel with a common source line electrically coupled to both, and a manufacturing method involving U-shaped channel structures with alternating insulating and conductive layers, where a slit is formed and filled with conductive layers to create a common source line, enabling easy formation of an I-shaped cell string structure and enhancing stack height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a common source line is formed in conventional three-dimensional memory structures, then capacitance and electrical characteristics are improved, but the manufacturing complexity and difficulty of forming the common source line in the pipe gate region increase
Solution Approach 1:
The common source line formation process is segmented into distinct stages: forming U-shaped channel structures with alternating insulating and conductive layers, creating slits at specific locations, and selectively filling slits with conductive material. This segmentation transforms a complex monolithic formation process into manageable discrete steps, reducing manufacturing complexity while achieving the desired electrical characteristics.
Solution Approach 2:
The patent transitions from conventional planar or simple vertical structures to U-shaped channel structures that extend in multiple dimensions. The common source line is formed by creating slits through alternating layers and filling them, utilizing vertical and lateral dimensions simultaneously. This dimensional approach enables precise positioning of the common source line in the pipe gate region while maintaining manufacturing feasibility.
2Volume of moving object
If cell strings are vertically formed to increase stack height, then memory capacity is improved, but the formation of common source lines and I-shaped structures becomes more difficult
Solution Approach 1:
The patent employs a nested structure where U-shaped channel structures are formed within alternating insulating and conductive layers. Slits are created within these nested layers, and conductive material is inserted into the slits to form the common source line. This nested approach allows the common source line to be integrated within the vertical stack without requiring separate formation processes, thereby maintaining ease of manufacture while achieving increased stack height.
Solution Approach 2:
The alternating insulating and conductive layers are formed preliminarily before the common source line is created. The U-shaped channel structures are prepared in advance with defined regions where slits will be formed. This preliminary structuring simplifies the subsequent common source line formation process, as the framework is already in place, making the overall manufacturing easier despite increased stack height.
3Shape
If U-shaped channel structures are used with alternating insulating and conductive layers, then I-shaped cell string structure is achieved, but the manufacturing process complexity increases
Solution Approach 1:
The patent merges the formation of U-shaped channel structures, alternating insulating and conductive layers, and common source line into a single integrated process sequence. The same alternating layer structure that creates the U-shaped channels also provides the framework for forming the common source line through slit creation and filling. This merging reduces overall manufacturing process complexity compared to forming these features separately, while achieving the desired I-shaped cell string structure.
Data Source
AI summary
Disclosed are a semiconductor device and a manufacturing method thereof. The semiconductor device includes source select lines, word lines, drain select lines, and a bit line stacked on a substrate in which a first cell string region and a second cell string region are defined; channel layers and memory layers vertically passing through the source select lines, the word lines, and the drain select lines in each of the first cell string region and the second cell string region; and a common source line vertically passing through the source select lines, the word lines, and the drain select lines at centers of the first cell string region and the second cell string region, and extended to a lower side of the source select lines.