Vertical Multi-Layer Computing Stack with Segmented Cooling
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Solution Overview
Problem
Conventional high performance computing systems face challenges with inefficient space usage, reduced performance due to horizontal die arrangements, and limited communication bandwidth, which hinder the achievement of high computing density and efficient cooling.
Innovation Solution
A vertical integrated power solution is implemented, where integrated circuit dies are arranged in a multi-layer structure with power and cooling delivered vertically and signals horizontally, utilizing System on Wafer (SoW) packaging to increase density and communication bandwidth, and incorporating multiple cooling systems for efficient thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If dies are arranged horizontally on a PCB, then ease of manufacture is improved, but computing density and space efficiency deteriorate
Solution Approach 1:
The patent transitions from traditional horizontal 2D arrangement of dies on a PCB to a vertical 3D stacked architecture. Multiple computing dies are arranged in vertical layers along the z-axis, with power and cooling systems integrated between layers. This dimensional change enables significantly higher computing density within the same footprint while maintaining manufacturability through standardized vertical stacking processes.
2Ease of manufacture
If dies are arranged horizontally on a PCB, then ease of manufacture is improved, but communication bandwidth and latency deteriorate
Solution Approach 1:
By stacking dies vertically, the patent creates multiple communication pathways between processing units. Data can be transmitted through vertical interconnects between layers as well as horizontal connections within layers, effectively increasing bandwidth. The reduced physical distance between dies in the vertical stack also decreases signal latency compared to horizontal arrangements.
3Volume of moving object
If computing density is increased, then space efficiency is improved, but cooling efficiency deteriorates
Solution Approach 1:
The patent divides the cooling system into multiple segmented cooling channels that are distributed between and within the vertical die layers. Each cooling channel independently manages thermal loads from adjacent dies, allowing for localized thermal control. This segmentation prevents heat accumulation and maintains cooling efficiency even as computing density increases.
Solution Approach 2:
The vertical stacking architecture enables three-dimensional thermal management, with cooling channels running both horizontally and vertically through the stack. Heat can be dissipated in multiple directions rather than being constrained to a single plane, significantly improving cooling efficiency for high-density configurations.
4Area of stationary object
If physical space is reduced, then computing density is improved, but manufacturing complexity increases
Solution Approach 1:
The vertical stacking approach packs more computing capacity into a smaller horizontal footprint by utilizing the vertical dimension. While the overall device complexity increases due to multiple layers, the manufacturing process is simplified through standardized stacking and interconnection techniques that can be automated, offsetting the increased structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances computational density, reduces physical space requirements, improves communication latency and bandwidth, and enables efficient cooling of high-density computing systems, suitable for applications like artificial intelligence and machine learning.
Implementation Method 1
a first cooling system disposed on top of and in thermal communication with the first electronics layer... a second cooling system disposed on top of and in thermal communication with the second electronics layer
Implementation Method 2
multiple cooling systems for efficient thermal management
Data Source
AI summary
The systems, methods, and devices disclosed herein relate to a multi-layer structures arranged in a vertically orientation. In some embodiments, a computing assembly can include a first cooling system, a first electronics layer, a second cooling system, and a second electronics layer. The first cooling system can be disposed on top of and can be in thermal communication with the first electronics layer. The first electronics layer array includes an array of integrated circuit dies that are in electronic communication with each other in a plane that is orthogonal to power delivery. The first electronics layer can be disposed on top of and can be in thermal communication with the second cooling system, and the second cooling system can be disposed on top of and can be in thermal communication with the second electronics layer. The second electronics layer includes an array of power delivery modules. In some embodiments, at least one layer can use system on wafer packaging.