Vertical Conductive Line for Semiconductor Memory Device Area Reduction
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Solution Overview
Problem
The miniaturization of semiconductor memory devices is limited by the size of the peripheral circuit structure and the lines connecting it to the memory cell array, which occupy significant area and hinder further integration.
Innovation Solution
The semiconductor memory device incorporates a vertical conductive line connected to both the peripheral circuit structure and the memory cell array, with gate stack structures and insulating layers, allowing for a more compact design by overlapping circuit groups and reducing the space required for the block word line, thereby minimizing the device's size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the peripheral circuit structure and connecting lines are arranged in a conventional two-dimensional layout, then the device can be manufactured with standard processes, but the device area becomes too large for further miniaturization
Solution Approach 1:
The patent transitions from a two-dimensional planar layout to a three-dimensional vertical architecture. The block word line is formed as a vertical conductive structure extending through multiple layers, and the peripheral circuit structures are stacked vertically above the memory cell array. This dimensional change allows circuit elements that would otherwise require significant lateral space to be compressed into the vertical dimension, thereby reducing the overall device footprint while maintaining functional complexity
Solution Approach 2:
The patent implements nested structures where peripheral circuit structures are positioned vertically above the memory cell array, with conductive patterns and insulating layers interleaved in multiple stacked layers. The block word line vertically penetrates through these nested structures, connecting different functional layers. This nesting arrangement allows multiple circuit functions to be integrated within a compact vertical column, significantly reducing the lateral area occupied by peripheral circuits
2Area of stationary object
If the block word line is formed as a conventional horizontal line, then the connection to pass transistors is straightforward, but the area occupied by connecting lines increases
Solution Approach 1:
The block word line is transformed from a horizontal two-dimensional conductor into a vertical three-dimensional structure that extends upward through multiple layers. This vertical orientation allows the block word line to connect to pass transistors in different lateral positions by simply varying the horizontal coordinates at different heights, eliminating the need for extensive lateral routing and reducing the area occupied by connecting lines
Solution Approach 2:
The block word line structure is segmented into multiple conductive patterns arranged vertically, with each segment connected to corresponding pass transistors at different locations. The vertical conductive line is divided into portions that can be independently formed and connected to different circuit blocks, simplifying the manufacturing process while reducing overall connecting line area
Data Source
AI summary
A semiconductor memory device includes a semiconductor substrate including a first circuit group and a second circuit group spaced apart from each other. The memory device also includes a memory cell array overlapping with the semiconductor substrate. The memory device further includes a vertical conductive line crossing the memory cell array, the vertical conductive line being connected to the first circuit group and the second circuit group.