Vertical Conductive Layer Layout for Shorter Signal Paths

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Solution Overview

Problem

Existing electronic devices face challenges in shortening the distance of signal transmission, which affects their performance and efficiency.

Innovation Solution

The manufacturing method involves a substrate with conductive layers and openings, a dielectric layer, and a chip configuration that allows for electrical coupling through a third conductive layer, enabling signal transmission at the shortest line distance across the substrate thickness.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If traditional signal transmission paths are used through the substrate, then signal transmission distance is long, but signal loss increases and performance deteriorates

Engineering Contradiction:
Improvesignal lossVSAvoidsignal transmission distance
Core Design Contradiction:
Loss of energyVSLength of moving object

Solution Approach 1:

The patent transitions from traditional planar signal transmission to three-dimensional vertical transmission by forming conductive layers (first conductive layer pattern, second conductive layer pattern, third conductive layer pattern) at different heights and positions. The signal travels vertically through stacked conductive structures rather than horizontally across the substrate surface, effectively shortening the transmission path and reducing signal loss through dimensional transformation.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent introduces dielectric layers as intermediary structures between conductive layers. These dielectric layers provide electrical insulation while maintaining structural integrity, enabling the formation of vertical conductive paths through the substrate. The dielectric layers act as mediators that allow signal transmission through controlled vertical pathways while preventing unwanted electrical interference between adjacent conductive elements.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Length of moving object

If conductive layers are added to shorten signal path, then signal transmission distance is reduced, but device complexity increases

Engineering Contradiction:
Improvesignal transmission distanceVSAvoidstructure complexity
Core Design Contradiction:
Length of moving objectVSDevice complexity

Solution Approach 1:

The patent divides the signal transmission path into multiple segmented conductive layers (first conductive layer pattern, second conductive layer pattern, third conductive layer pattern) positioned at different vertical levels. Each conductive layer segment performs a specific function in the overall signal transmission pathway, allowing the complex transmission task to be broken down into manageable segments that can be independently optimized and manufactured.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The conductive layers serve multiple functions simultaneously: they provide electrical conduction pathways, establish vertical interconnections between different substrate surfaces, provide structural support for the stacked architecture, and enable electrical coupling between chips and substrate circuits. This multi-functionality reduces the need for separate dedicated structures for each function, thereby managing complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20260012221A1Electronic device
Publication Date: 2026.01.08 INNOLUX CORP
  • US20260012221A1 patent drawing
  • US20260012221A1 patent drawing
  • US20260012221A1 patent drawing

AI summary

An electronic device includes a substrate, a first conductive layer pattern, a second conductive layer pattern, a first opening, a dielectric layer, a third conductive layer pattern and a chip. The first conductive layer pattern is disposed on a surface of the substrate. The second conductive layer pattern is disposed on another surface of the substrate. The another surface is opposite to the surface. The first opening penetrates the surface and the another surface. The dielectric layer is disposed on the surface and covers the first conductive layer pattern. The third conductive layer pattern is disposed on the dielectric layer and electrically coupled to the first conductive layer pattern through a second opening penetrated the dielectric layer. The chip is disposed on the substrate and electrically coupled to the third conductive layer pattern through a first solder ball. The second opening tapers toward and misalign with the first opening.