Vertical Conical Frustum Gate-All-Around Transistor
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Solution Overview
Problem
The scaling down of CMOS transistors faces challenges due to rapidly increasing power consumption caused by off-state current leakage, which is attributed to the decreasing thickness of the gate oxide film, necessitating a method for further transistor scaling.
Innovation Solution
A method involving the fabrication of a device with a vertical conical frustum structure and a gate all-around (GAA) configuration, where a drain is formed at the bottom and a source at the top, with a GAA structure that overlaps with both, using a series of lithography, etching, and ion implantation processes to manage dopant distribution and oxide layers, facilitating efficient transistor scaling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the gate oxide film thickness is decreased to enable transistor scaling, then the transistor size is reduced, but the off-state current leakage increases causing higher power consumption
Solution Approach 1:
The patent transitions from planar gate structures to three-dimensional FinFET and nanosheet structures. By verticalizing the channel and creating fins or sheets that extend upward from the substrate, the device utilizes the third dimension to increase effective channel area while maintaining a small footprint. This dimensional change allows better gate control over the channel and reduces off-state leakage without simply scaling down the gate oxide thickness further.
Solution Approach 2:
The gate structure completely surrounds the channel region in FinFET and nanosheet configurations. The gate wraps around the channel from multiple sides, creating a nested configuration where the gate is positioned on all four sides of the channel. This nested arrangement provides superior electrostatic control compared to planar gates, enabling effective suppression of off-state current while maintaining scaled dimensions.
2Length of moving object
If the gate oxide film thickness is decreased to enable further transistor scaling, then smaller geometry is achieved, but the manufacturing complexity increases
Solution Approach 1:
The fabrication process is divided into distinct sequential stages: forming the sacrificial mandrel structure, depositing and patterning spacer layers, selectively removing portions to create fins or nanosheets, and forming the gate structure. Each stage produces a well-defined intermediate structure that simplifies the next step. This segmentation of the complex nanoscale fabrication into manageable discrete steps reduces overall manufacturing complexity despite the advanced geometry being created.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach helps in reducing power consumption and enabling further scaling of transistors by effectively managing the off-state current leakage through precise control of dopant distribution and oxide layers, enhancing the complexity and efficiency of transistor processing.
Implementation Method 1
a first ion implantation process to form a p-type well in the semiconductor substrate, and a second ion implantation process to form an n-type well in the semiconductor substrate
Data Source
AI summary
A device includes a wafer substrate, a conical frustum structure formed in the wafer substrate, and a gate all-around (GAA) structure circumscribing the middle portion of the conical frustum structure. The conical frustum structure includes a drain formed at a bottom portion of the conical frustum, a source formed at a top portion of the vertical conical frustum, and a channel formed at a middle portion of the conical frustum connecting the source and the drain. The GAA structure overlaps with the source at one side of the GAA structure, crosses over the channel, and overlaps with the drain at another side of the GAA structure.