Stacked Solid-State Imaging Layout for Low Parasitic Capacitance
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Solution Overview
Problem
In solid-state imaging devices with a three-dimensional structure, wiring capacitance (parasitic capacitance) in the conductive path between semiconductor layers reduces photoelectric conversion efficiency.
Innovation Solution
A solid-state imaging device design where a contact electrode extends vertically through both semiconductor layers and is directly connected to the source region of a switching transistor, the gate electrode of amplification transistors, and the charge holding region, eliminating horizontal wiring and thus reducing wiring capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conductive path including contact electrode and wiring is used to electrically connect charge holding region and pixel transistor in stacked semiconductor layers, then electrical connection is achieved, but wiring capacitance is added which decreases photoelectric conversion rate
Solution Approach 1:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked structure. The contact electrode extends vertically through multiple semiconductor layers to directly connect the charge holding region in the first layer with the pixel transistor in the second layer, eliminating the need for horizontal wiring and thereby reducing wiring capacitance while maintaining electrical connection.
Solution Approach 2:
The patent extracts and eliminates the wiring component from the conductive path. By using a contact electrode that extends vertically through the semiconductor layers, the design removes the horizontal wiring that previously contributed to wiring capacitance, achieving direct connection between functional elements across layers.
2Productivity
If multiple semiconductor layers are stacked to increase element density, then number of elements increases, but wiring capacitance in conductive paths increases reducing photoelectric conversion efficiency
Solution Approach 1:
The patent utilizes vertical stacking of semiconductor layers to increase element density while maintaining low wiring capacitance. By extending the contact electrode vertically through the stacked layers for direct connection, the design achieves high element density without the penalty of increased horizontal wiring capacitance that would reduce photoelectric conversion efficiency.
Solution Approach 2:
The patent divides the semiconductor device into multiple stacked layers, with the contact electrode segmented to extend through each layer. This segmentation allows independent optimization of each layer while maintaining efficient vertical electrical connection, achieving high element density with minimal wiring capacitance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances photoelectric conversion efficiency by minimizing wiring capacitance and allowing for faster readout of signal charges, improving the overall performance of the imaging device.
Implementation Method 1
a photoelectric conversion part provided in the first semiconductor layer; a charge holding region provided in the first semiconductor layer and configured to accumulate a signal charge generated by photoelectric conversion performed by the photoelectric conversion part
Data Source
AI summary
The purpose of the present technology is to improve photoelectric conversion efficiency. A first semiconductor layer, a second semiconductor layer on a side of the first semiconductor layer remote from a light incident surface, a photoelectric conversion part in the first semiconductor layer, a charge holding region in the first semiconductor layer and configured to accumulate a signal charge generated by photoelectric conversion performed by the photoelectric conversion part, first and second field effect transistors each including a gate electrode and a pair of main electrode regions, each of the pairs of main electrode regions being provided in the second semiconductor layer, and a contact electrode extending through the first and second semiconductor layers and directly connected to any one of the pair of main electrode regions of the first field effect transistor, the gate electrode of the second field effect transistor, and the charge holding region are included.