Vertical Metallic Contacts for High-Voltage Semiconductor Packaging
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Solution Overview
Problem
Current chip embedding processes do not meet high voltage application requirements due to limitations in breakdown voltage, halogen impurity levels, and reliability of PCB materials, as well as a limited isolation distance between the chip edge and the routing layer.
Innovation Solution
A semiconductor device module with embedded vertical metallic contacts that extend through an encapsulant to connect semiconductor die contact pads with outer metallic contact layers, allowing for improved electrical connectivity and reduced parasitic inductances, and a method for fabricating this module by pre-fabricating semiconductor die packages for optimal interaction and isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If current PCB materials and chip embedding processes are used, then manufacturing simplicity is maintained, but breakdown voltage and reliability are insufficient for high voltage applications
Solution Approach 1:
The module is divided into distinct functional layers: semiconductor die, encapsulant material, and PCB substrate. This segmentation allows each component to be optimized independently for high voltage performance while maintaining manufacturability through standardized assembly processes.
Solution Approach 2:
An encapsulant material layer is introduced as an intermediary between the semiconductor die and the PCB substrate. This encapsulant provides electrical isolation and mechanical protection, enabling high voltage operation by preventing direct contact and potential breakdown paths between conductive elements.
2Reliability
If standard chip embedding processes are used, then device complexity is low, but isolation distance between chip edge and routing layer is limited to 50-100 μm
Solution Approach 1:
The electrical connection path is transitioned from a planar routing layout to a vertical three-dimensional configuration. Vertical conductive vias extend through the encapsulant layer, providing direct electrical connection between the semiconductor die contact pads and the PCB routing layers, thereby eliminating the need for extended lateral isolation distances.
Solution Approach 2:
The encapsulant material serves as an intermediary that provides electrical isolation in the vertical dimension. By establishing isolation through the thickness of the encapsulant layer rather than through lateral spacing, the design achieves greater isolation distances without increasing device footprint or complexity.
3Power
If vertical metallic contacts extending through encapsulant are used, then parasitic inductances are reduced and power handling capability is improved, but manufacturing precision requirements increase
Solution Approach 1:
Conductive vias are formed and prepared in the encapsulant material before the semiconductor die is mounted. This preliminary action establishes the vertical connection pathways in advance, allowing for precise alignment and reducing the precision requirements during the subsequent die attachment process.
Solution Approach 2:
The encapsulant material with pre-formed conductive vias serves as a self-aligning structure. The via locations and dimensions are designed to automatically guide and accommodate the semiconductor die contact pads, reducing the need for high-precision manual alignment during assembly.
Data Source
AI summary
A semiconductor device module includes a package carrier having an opening, wherein in the opening there is disposed a semiconductor package including a semiconductor die, an encapsulant, and first vertical contacts, wherein the encapsulant at least partially covers the semiconductor die, and the first vertical contacts are connected to the semiconductor die and extend at least partially through the encapsulant, and a first outer metallic contact layer electrically connected to the first vertical contacts.