Vertical Core 3D Transistor Structure for Dense Routing
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to increase transistor density beyond the limitations of two-dimensional (2D) circuits, as scaling efforts face difficulties in single-digit nanometer semiconductor device fabrication nodes, and there is a need for three-dimensional (3D) integration to enhance packing density and routing capabilities.
Innovation Solution
The use of a vertical dielectric core for 3D semiconductor device fabrication, enabling metal routing and connections, and allowing for high packing density through multiple 360-degree metal routing shells, with separate gate biasing capabilities and differential channel lengths, along with specific manufacturing steps to form buried power rail and interconnect structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 2D circuit fabrication is used, then manufacturing process is simple, but transistor density is limited
Solution Approach 1:
The patent transitions from 2D planar circuits to 3D vertical circuits by stacking multiple transistor layers vertically. This dimensional change enables significantly higher transistor density within the same footprint area, as transistors are arranged in three-dimensional space rather than confined to a single plane.
Solution Approach 2:
The patent implements nested structures where multiple transistor layers are stacked vertically, with each layer containing transistors that are vertically aligned with layers below. This nesting approach maximizes the use of vertical space to increase overall transistor density while maintaining a compact form factor.
2Quantity of substance
If 3D vertical stacking is implemented, then transistor density increases, but routing complexity increases
Solution Approach 1:
The patent segments the routing function into multiple independent metal layers, each handling specific interconnect tasks. This segmentation allows complex 3D routing to be broken down into manageable layers, reducing overall routing complexity while supporting high transistor density through systematic interconnect organization.
Solution Approach 2:
The patent introduces multiple metal routing layers stacked vertically to provide three-dimensional routing capabilities. This vertical routing dimension enables direct connections between vertically stacked transistors, significantly simplifying interconnect paths compared to lateral routing in 2D circuits and reducing overall routing complexity.
3Quantity of substance
If scaling to single-digit nanometer nodes is pursued, then transistor size decreases, but manufacturing precision requirements increase
Solution Approach 1:
The patent moves fabrication from 2D planar processes to 3D vertical processes, enabling continued transistor density improvement without proportionally increasing manufacturing precision requirements. The vertical stacking approach allows standard lithographic processes to achieve higher densities through three-dimensional structuring rather than requiring extreme precision at single-digit nanometer scales.
Data Source
AI summary
A semiconductor device includes a buried power rail (BPR) over a substrate and a semiconductor structure over the BPR. The semiconductor structure is tube-shaped and extends along a vertical direction. The semiconductor structure includes a first source/drain (S/D) region over the BPR, a gate region over the first S/D region, and a second S/D region over the gate region. The semiconductor device includes a first S/D interconnect structure extending from the BPR and further into the semiconductor structure such that a top portion of the first S/D interconnect structure is surrounded by the first S/D region. The semiconductor device includes a gate structure that includes (i) a gate oxide formed along an inner surface of the gate region and (ii) a gate electrode formed along sidewalls of the gate oxide in the gate region. The semiconductor device includes a second S/D interconnect structure positioned over the second S/D region.