Self-Aligned Vertical Solid-State Fabrication for Precise Substrate Bonding
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Solution Overview
Problem
The existing methods for fabricating vertical solid state devices, such as LEDs, are complex and costly, requiring multiple photolithography steps with high chances of inaccuracies, and face challenges in aligning and hermetically bonding substrates with different sizes and thermal expansion coefficients, leading to reduced yields and performance issues.
Innovation Solution
A self-aligned fabrication process that simplifies photolithography by using a single lithography step, depositing device layers with ohmic contact layers, and selectively etching the doped conductive layers without etching the active layers, along with a bonding process that aligns microdevices with system substrates having larger contact pads, ensuring uniform and reliable hermetic sealing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple photolithography steps are used to fabricate microLED devices, then device patterning can be achieved, but manufacturing complexity increases and alignment accuracy decreases
Solution Approach 1:
The patent combines multiple photolithography steps into a single lithography step by using a self-aligned fabrication process. The method forms a first conductive layer, patterns it, then uses the same patterned layer as a mask to form a second conductive layer, eliminating the need for separate masking steps and achieving perfect alignment between different conductive structures.
Solution Approach 2:
The fabrication process uses self-alignment where previously deposited and patterned layers serve as their own masks for subsequent deposition steps. The patterned first conductive layer automatically defines the alignment for the second conductive layer, eliminating the need for external mask alignment and reducing manufacturing complexity.
2Adaptability or versatility
If substrates with different sizes and thermal expansion coefficients are bonded, then device integration is achieved, but bonding reliability and hermetic sealing become difficult
Solution Approach 1:
The patent applies local quality by creating a gradient in the adhesive layer thickness. The adhesive layer is thinner at the center of the bond interface and thicker at the edges, which compensates for thermal expansion mismatches between substrates of different materials and sizes. This localized variation in adhesive properties ensures uniform stress distribution and reliable hermetic bonding despite substrate differences.
3Productivity
If microdevices are patterned to micro size for display applications, then device density increases, but material utilization decreases and defect creation increases
Solution Approach 1:
The patent uses preliminary action by forming a complete patterned conductive layer before depositing subsequent layers. The first conductive layer is fully patterned using a single lithography step, and this completed pattern serves as a template for the second conductive layer. This approach maximizes material utilization by ensuring that materials are deposited only where needed, reducing waste while achieving high device density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances production yield by eliminating misalignment issues, reduces fabrication costs, and achieves high-quality, bubble-free bonding between microdevices and system substrates, improving the performance and efficiency of vertical solid state devices.
Implementation Method 1
depositing a plurality of device layers on the semiconductor substrate, depositing an ohmic contact layer on an upper surface of one of the plurality of device layers
Implementation Method 2
selectively etching down the doped conductive layer that does not substantially etch the active layer
Data Source
AI summary
Various embodiments include methods of fabricating an array of self-aligned vertical solid state devices and integrating the devices to a system substrate. The method of fabricating a self-aligned vertical solid state device comprising: providing a semiconductor substrate, depositing a plurality of device layers on the semiconductor substrate, depositing an ohmic contact layer on an upper surface of one of the plurality of device layers, wherein the device layers comprises an active layer and a doped conductive layer, forming a patterned thick conductive layer on the ohmic contact layer; and selectively etching down the doped conductive layer that does not substantially etch the active layer.