Vertical Die-to-Die Interconnects for Compact High Die Stacks
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Solution Overview
Problem
Conventional semiconductor packages face challenges in maintaining signal integrity, managing thermal dissipation, and ensuring reliable power delivery as they become denser, with increasing integration of dies leading to space constraints and complex interconnections.
Innovation Solution
The implementation of vertical die-to-die interconnects in high die stack packages, allowing for a cascading arrangement of dies with reduced lateral dimensions, utilizing wire bonds and vertical wires to connect stacked dies directly to a substrate or an input-and-output extender, while maintaining electrical reliability and thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional packaging processes are used with increasing die integration, then die density increases, but lateral dimensions increase and interconnection complexity increases
Solution Approach 1:
The patent transitions from conventional lateral interconnections to vertical interconnections by stacking dies in the Z-dimension. Multiple dies are arranged in a cascading stack configuration with vertical wires providing interconnects between adjacent dies, enabling high die integration density while maintaining compact lateral footprint.
2Area of stationary object
If dies are stacked vertically with vertical interconnects, then lateral dimensions are reduced, but manufacturing complexity increases
Solution Approach 1:
The patent divides the package into discrete die stacks, each containing multiple dies connected by vertical wires. The cascading arrangement segments the vertical space into manageable layers, with each die stack forming an independent module that can be manufactured and assembled systematically.
Solution Approach 2:
The patent performs preliminary actions by forming vertical wires and establishing electrical connections between dies before final package assembly. Wire bonds are attached to bond pads on each die, and vertical interconnects are established in advance, enabling subsequent encapsulation and finishing operations.
3Device complexity
If conventional lateral interconnections are used, then signal routing is simple, but thermal dissipation becomes difficult as density increases
Solution Approach 1:
The patent introduces vertical heat dissipation pathways by stacking dies with vertical interconnects. This three-dimensional arrangement creates additional thermal conduction paths through the stack, enabling more efficient heat removal from high-density die configurations compared to conventional lateral arrangements.
4Area of stationary object
If vertical die stacking with cascading arrangement is implemented, then space requirements are reduced, but electrical integrity maintenance becomes more challenging
Solution Approach 1:
The patent uses vertical wires as intermediary conductors to establish electrical connections between bond pads on different dies. These vertical interconnects serve as mediators that transmit signals and power through the stacked die structure, maintaining electrical integrity despite the increased vertical complexity.
Data Source
AI summary
Systems, devices, and methods for high die stack packages with vertical die-to-die interconnects are provided herein. A die stack package can include a substrate, a lower die stack carried by the substrate, a spacer carried by the substrate, an upper die stack carried by the spacer, a plurality of wire bonds, and a plurality of vertical wires. The lower die stack can include a plurality of lower dies stacked in a cascading arrangement. The upper die stack can include a plurality of upper dies stacked in a cascading arrangement in a same direction as the plurality of lower dies. The wire bonds can electrically couple adjacent ones of the lower dies. An nth vertical wire can extend vertically between and electrically couple an nth upper die and an nth lower die. In some embodiments, the die stack package further includes an input-and-output extender carried by the substrate.