Vertical Diffusion Plate Capacitor Layout for Dense 3D NAND
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Solution Overview
Problem
Conventional capacitors in 3D NAND technology require large chip areas and metal trace spaces, leading to space constraints and time-dependent dielectric breakdown issues as the number of devices and traces increase, necessitating a novel capacitor structure that occupies minimal space while maintaining high capacitance.
Innovation Solution
A capacitor structure with vertically-arranged diffusion plates in a silicon substrate, utilizing shallow trench isolation and wafer-backside trench isolation structures to efficiently isolate and couple diffusion plates, forming a capacitor dielectric layer and increasing capacitance per unit area without occupying excessive space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional MOS capacitors or MOM capacitors are used to provide voltage boosting in 3D NAND, then the capacitance requirement is met, but the chip area and metal trace area occupied is large
Solution Approach 1:
The patent transitions from planar capacitor structures to vertically stacked diffusion plates embedded in the silicon substrate. By utilizing the vertical dimension (z-axis) with multiple diffusion plates stacked at different depths, the capacitor achieves high capacitance without occupying excessive chip area. The diffusion plates are arranged vertically with isolation structures between them, enabling three-dimensional integration within the substrate volume.
2Quantity of substance
If large-area MOS capacitors are used to achieve required capacitance, then the capacitance target is met, but time-dependent dielectric breakdown (TDDB) problems occur
Solution Approach 1:
The patent divides the capacitor structure into multiple discrete diffusion plates separated by isolation structures. Instead of using a single large-area capacitor, the total capacitance is distributed across multiple smaller diffusion plates stacked vertically. Each diffusion plate is isolated from others by STI or other isolation structures, which prevents dielectric breakdown from propagating across the entire capacitor area and improves overall reliability.
3Productivity
If the number of devices and traces is increased to achieve higher storage density, then the storage capacity increases, but the space for silicon wafer and back-end routing becomes smaller
Solution Approach 1:
The patent integrates capacitors vertically within the silicon substrate using stacked diffusion plates, rather than placing them in the planar routing layer. This vertical integration frees up the back-end routing space for additional traces and interconnects, enabling higher device density and storage capacity without compromising routing capability.
Data Source
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AI summary
A capacitor structure includes a semiconductor substrate, a first vertical diffusion plate disposed in the semiconductor substrate, a first shallow trench isolation (STI) structure disposed in the semiconductor substrate and surrounding the first vertical diffusion plate, and a second vertical diffusion plate disposed in the semiconductor substrate and surrounding the first STI structure. The first vertical diffusion plate further includes a first lower portion that is part of the semiconductor substrate. The first lower portion is surrounded and electrically isolated by a first wafer-backside trench isolation structure. The first wafer-backside trench isolation structure is in direct contact with a bottom of the first STI structure.