Vertical Digit Line Layout for Stacked DRAM Cell Density
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Solution Overview
Problem
As design rules shrink, less semiconductor space is available for fabricating memory devices, particularly DRAM arrays, leading to challenges in integrating memory cells with efficient access and storage structures.
Innovation Solution
The integration of vertically oriented digit lines with horizontally oriented access devices and access lines in vertically stacked memory cells, utilizing a gate all around (GAA) structure for improved electrostatic control and reduced digit line capacitance, along with thinner channel regions for better subthreshold slope and cost-effectiveness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If design rules are shrunk to increase memory density, then memory capacity is improved, but available semiconductor space for access structures is reduced
Solution Approach 1:
The patent transitions from planar (2D) memory cell layouts to vertically stacked (3D) memory cells with digit lines extending in the vertical direction. This dimensional change allows memory cells to be stacked above each other, dramatically increasing memory capacity per unit area while preserving adequate space for access structures in the horizontal plane.
2Loss of energy
If vertical digit lines are implemented with horizontally oriented access devices, then digit line capacitance is reduced, but fabrication complexity increases
Solution Approach 1:
The patent segments the digit lines into vertical portions that pass through multiple stacked memory cell layers. This segmentation allows the digit lines to be formed as separate vertical structures rather than continuous horizontal lines, reducing capacitance by minimizing overlap with charged regions while enabling modular fabrication processes.
Solution Approach 2:
The patent implements a nested structure where vertically oriented digit lines pass through horizontally oriented access devices and memory cell layers. The digit lines are positioned within or adjacent to the vertical stacks, creating a nested arrangement that reduces capacitance while maintaining compact fabrication sequences.
3Reliability
If gate all around (GAA) structure is used for vertically stacked memory cells, then electrostatic control is improved, but manufacturing complexity increases
Solution Approach 1:
The patent employs gate all around (GAA) structures where the gate electrode completely surrounds the channel region in three dimensions, providing superior electrostatic control compared to planar gates. This 3D gating structure is integrated into vertically stacked memory cells, enabling better threshold voltage control and reduced leakage, while the fabrication process builds upon existing vertical stacking techniques.
Data Source
AI summary
Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and access lines and vertically oriented digit lines having a first source/drain region and a second source drain region separated by a channel region, and gates opposing the channel region formed fully around every surface of the channel region as gate all around (GAA) structures, horizontal oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source/drain region and vertically oriented digit lines coupled to the first source/drain regions. A vertical body contact is formed in direct electrical contact with a body region of one or more of the horizontally oriented access devices and separate from the first source/drain region and the vertically oriented digit lines by a dielectric.