Vertical Digit Line Layout for Stacked DRAM Signal Integrity
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Solution Overview
Problem
As design rules shrink, less semiconductor space is available for fabricating memory devices, particularly DRAM arrays, leading to challenges in integrating memory cells with efficient access and storage nodes.
Innovation Solution
A vertically oriented digit line is integrated with horizontally oriented access devices and access lines in an array of vertically stacked memory cells, utilizing a gate all around (GAA) structure for better electrostatic control and lower capacitance, along with thinner channel materials for improved geometry and voltage signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional horizontal digit lines are used in planar DRAM arrays, then manufacturing process is simpler, but digit line capacitance is high and voltage signal integrity deteriorates
Solution Approach 1:
The patent transitions from traditional planar (2D) digit lines to vertically oriented (3D) digit lines that extend through multiple memory cell layers. This dimensional change reduces the horizontal routing distance and minimizes parasitic capacitance between digit lines and other structures, thereby improving voltage signal integrity while managing the increased structural complexity through systematic vertical stacking
2Productivity
If design rules are shrunk to increase memory density, then more memory cells fit in available space, but digit line capacitance increases and voltage signal integrity worsens
Solution Approach 1:
By stacking memory cell arrays vertically and orienting digit lines in the vertical direction, the patent achieves higher memory density without proportionally increasing digit line capacitance. The vertical orientation allows digit lines to serve multiple layers simultaneously, reducing the total capacitance per bit compared to scaled planar designs where digit lines must be shortened and replicated across each layer
Solution Approach 2:
The patent divides the memory array into multiple stacked layers, each with its own set of access devices and shared digit lines. This segmentation allows the digit lines to be optimized for vertical routing rather than horizontal scaling, maintaining lower capacitance values even as total memory capacity increases through additional layers
3Reliability
If Gate All Around (GAA) structure with thinner channel material is implemented, then electrostatic control and subthreshold slope improve, but manufacturing complexity increases
Solution Approach 1:
The GAA structure implements a three-dimensional gate configuration where the gate electrode completely surrounds the channel in the vertical direction, providing superior electrostatic control compared to planar gates. This vertical gating approach achieves better subthreshold slope and threshold voltage control, though it requires more complex fabrication steps including sequential deposition and patterning of alternating semiconductor and dielectric layers
Data Source
AI summary
Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and access lines and vertically oriented digit lines having a first source/drain region and a second source drain region separated by a channel region, and gates opposing the channel region formed fully around every surface of the channel region as gate all around (GAA) structures, horizontal oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source/drain region and vertically oriented digit lines coupled to the first source/drain regions. A vertical body contact is formed in direct electrical contact with a body region of one or more of the horizontally oriented access devices and separate from the first source/drain region and the vertically oriented digit lines by a dielectric.