Vertical Digit Lines With Epitaxial Silicon for Low-Leakage 3D Memory
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Solution Overview
Problem
As design rules shrink, less semiconductor space is available for fabricating memory devices, leading to issues with current leakage through polycrystalline silicon in DRAM arrays, which affects transistor performance and efficiency.
Innovation Solution
The use of alternating epitaxially grown silicon germanium and silicon layers forms horizontal access devices in vertical 3D memory, utilizing a silicon wafer as a substrate for single crystal silicon growth, which reduces leakage by eliminating grain boundaries and improving electrostatic control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If polycrystalline silicon is used in DRAM arrays, then manufacturing is easier and cost is lower, but current leakage increases and transistor performance deteriorates
Solution Approach 1:
The patent changes the material parameter from polycrystalline silicon to single-crystal silicon, fundamentally altering the crystal structure to eliminate grain boundaries. This parameter change resolves the contradiction by providing both low leakage (high reliability) and maintaining manufacturability through established single-crystal growth techniques
Solution Approach 2:
The patent employs a composite structure with alternating layers of silicon germanium and silicon materials. This composite approach enables selective etching processes while maintaining the benefits of single-crystal silicon, resolving the contradiction between performance and manufacturing complexity
2Productivity
If design rules are shrunk to increase memory density, then more memory can be fabricated in less space, but current leakage through polycrystalline silicon increases
Solution Approach 1:
By changing from polycrystalline to single-crystal silicon, the patent eliminates the grain boundary leakage path that becomes particularly problematic at scaled dimensions. This parameter change enables high memory density to be achieved without the leakage penalties that would otherwise occur
Solution Approach 2:
The patent segments the silicon material into alternating layers of silicon germanium and silicon, creating a structured composite that maintains single-crystal benefits while enabling selective processing. This segmentation allows the structure to scale to higher densities without suffering from polycrystalline leakage issues
3Reliability
If alternating epitaxially grown silicon germanium and silicon layers are formed, then leakage is reduced and transistor performance is improved, but manufacturing process complexity increases
Solution Approach 1:
The silicon germanium layers serve as intermediary sacrificial structures that enable the formation of single-crystal silicon regions. These intermediary layers are selectively etched away to create the desired device structure, resolving the contradiction by providing a manufacturable path to the low-leakage single-crystal configuration
Solution Approach 2:
The patent applies different material properties locally through alternating layers of silicon germanium and silicon. The silicon germanium layers provide selective etchability while the silicon layers provide the low-leakage channel, with each layer having optimized local properties that resolve the overall contradiction between performance and complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in lower off-current, better DRAM refresh requirements, and reduced gate/drain induced leakage, enhancing transistor performance and efficiency.
Implementation Method 1
alternating epitaxially grown silicon germanium and silicon layers forms horizontal access devices in vertical 3D memory, utilizing a silicon wafer as a substrate for single crystal silicon growth
Data Source
AI summary
Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes. The horizontally oriented access devices having a first source/drain regions and a second source drain regions separated by silicon (Si) channel regions. A digit line having a global digit line (GDL) contact is formed in a trench adjacent to the first source/drain regions. In one example, the digit line is electrically isolated from a neighboring digit line at the bottom of the trench. In another example, the digit line is formed continuously along a bottom surface of trench to form shared digit lines between horizontal access devices, in two separate arrays, on opposing second vertical surfaces. The memory cells have horizontally oriented storage nodes coupled to the second source/drain regions and vertical digit lines coupled to the first source/drain regions.