Vertical Diode Layout for ESD Protection in Dense ICs
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Solution Overview
Problem
ESD events can damage semiconductor-based devices by exceeding their voltage tolerance, and existing ESD protection methods consume valuable surface area and require connections between the front and back sides of semiconductor wafers, leading to thicker devices.
Innovation Solution
Vertical diodes with front and back contacts are arranged within the device plane, utilizing a p-n junction formed by semiconductor regions, allowing for efficient ESD protection with minimal surface area consumption and reduced device thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing ESD protection methods are used, then ESD protection is provided, but surface area is consumed and device thickness increases
Solution Approach 1:
The patent transitions from planar ESD protection structures to vertical three-dimensional structures. The ESD diode is formed with a first contact on the front surface and a second contact on the back surface, utilizing the vertical dimension through the substrate. This dimensional change allows ESD protection functionality to be achieved without consuming additional lateral surface area, as the protection path extends through the thickness of the device rather than across its surface.
2Reliability
If existing ESD protection methods are used, then ESD protection is provided, but device thickness increases
Solution Approach 1:
The vertical ESD diode structure serves multiple functions within a compact footprint. The same vertical path that provides ESD protection also enables back-side contact access for the diode terminal, eliminating the need for separate lateral routing paths. This multi-functionality allows the ESD protection mechanism to be integrated without proportionally increasing device thickness, as the protection current path coincides with the contact structure.
3Area of stationary object
If vertical diodes with front and back contacts are used, then surface area is minimized and thickness is reduced, but ESD protection effectiveness must be maintained
Solution Approach 1:
The patent modifies the geometric parameters of the ESD protection structure by changing from a lateral/planar configuration to a vertical configuration. The diode junction depth, contact pad sizes, and substrate thickness are optimized parameters that ensure adequate ESD protection capability is achieved within the constrained vertical space. By controlling the depth of the p-n junction and the dimensions of the front and back contacts, the patent maintains sufficient protection effectiveness while minimizing surface area consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The vertical diodes effectively protect against ESD events while maintaining device density and reducing the overall thickness of integrated circuit packages.
Implementation Method 1
utilizing a p-n junction formed by semiconductor regions
Data Source
AI summary
Vertical diodes are included in a device plane of an integrated circuit device, e.g., a diode array is in the same plane as a transistor array. The vertical diodes are semiconductor diodes, or p-n diodes, that have two contacts stacked vertically over and under the diode. The vertical diodes may be formed around a fin, e.g., with a front-side contact over the fin and a back-side contact under the fin. One or more diodes may be electrically coupled to a transistor to provide electrostatic discharge protection.