Vertical Diode Fabrication via Low-Temperature Ion Implantation

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Solution Overview

Problem

As semiconductor devices become highly integrated, there is a need to reduce the area occupied by their elements, and existing methods struggle to efficiently form vertical diodes without high-temperature processes that can degrade the semiconductor substrate.

Innovation Solution

A method of fabricating semiconductor devices that includes forming well and impurity regions in a semiconductor substrate, etching to create specific patterns, and using a metal-semiconductor compound layer to improve electrical characteristics, all while avoiding high-temperature processes like selective epitaxial growth.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If selective epitaxial growth is used to form vertical diodes, then the diode structure can be formed, but the semiconductor substrate is degraded due to high temperature processing

Engineering Contradiction:
Improvesubstrate integrityVSAvoidprocessing temperature
Core Design Contradiction:
ReliabilityVSTemperature

Solution Approach 1:

The patent changes the temperature parameter from high-temperature selective epitaxial growth to low-temperature ion implantation and thermal annealing processes. Specifically, ion implantation is performed at room temperature or low temperature, followed by rapid thermal annealing at moderate temperatures (e.g., 600-900°C for short durations), which forms the vertical diode structure without subjecting the substrate to prolonged high-temperature exposure that would cause degradation.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If element area is reduced for high integration, then device density increases, but manufacturing precision becomes more difficult to maintain

Engineering Contradiction:
Improvedevice integration densityVSAvoidpattern formation accuracy
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent transitions from planar diode structures to vertical diode structures by adding the depth dimension. The diode is formed with a vertical junction extending from the surface into the substrate, allowing the active area to be concentrated in a vertical column rather than spread horizontally. This enables higher integration density while maintaining adequate manufacturing precision through standardized photolithography and ion implantation processes.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent applies local quality by creating highly doped regions (e.g., n+ and p+ regions) in specific localized areas through ion implantation. The impurity concentration is dramatically increased in the vertical diode regions compared to surrounding areas, enabling precise control of electrical characteristics at the desired location without affecting adjacent structures, thus maintaining manufacturing precision even as device density increases.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for the formation of vertical diodes without degrading the semiconductor substrate and enhances the electrical performance of word lines by forming metal-semiconductor compounds, improving the overall efficiency and reliability of semiconductor devices.

Implementation Method 1

forming metal-semiconductor compounds

Methodology Applied
Scientific EffectChemical reaction: Chemical Bonding

Data Source

PatentUS8143150B2Method of fabricating semiconductor device and electronic system
Publication Date: 2012.03.27 SAMSUNG ELECTRONICS CO LTD
  • US8143150B2 patent drawing
  • US8143150B2 patent drawing
  • US8143150B2 patent drawing

AI summary

A method of fabricating a semiconductor device includes forming a well impurity region, a lower impurity region and an upper impurity region in a semiconductor substrate. The lower impurity region has a different conductivity type than a conductivity type of the well impurity region, the upper impurity region has a different conductivity type than the conductivity type of the lower impurity region, and the upper impurity region has a same conductivity type as the conductivity type of the well impurity region and has a higher impurity concentration than an impurity concentration of the well impurity region. The semiconductor substrate is etched to form lower semiconductor patterns, upper semiconductor patterns upwardly projecting from predetermined regions of the lower semiconductor patterns. An isolation layer filling the first and second spaces between the lower semiconductor patterns and between the upper semiconductor patterns, respectively is formed.