Vertical Diode Polysilicon Crystallization via Metal Silicide
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Solution Overview
Problem
The existing methods for forming polysilicon layers in semiconductor devices, such as phase-change memory devices, face challenges in achieving stable driving currents due to damage to the active region and interface stress in multilayer structures, leading to inferior crystalline characteristics and high internal resistance.
Innovation Solution
A method involving the formation of an amorphous silicon layer using a CVD process, followed by crystallization using a metal silicide layer at a relatively low temperature to form a polysilicon layer, which reduces thermal budget and leakage currents, and subsequent implantation of impurities to create a doped polysilicon layer for a vertical diode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a selective epitaxial growth process is used to form a polysilicon layer, then the polysilicon layer can be formed on the substrate, but the active region exposed by the opening is damaged and interface stress is generated in multilayer structures, leading to inferior crystalline characteristics
Solution Approach 1:
An amorphous silicon layer is formed in advance to fill the opening and protect the active region before the polysilicon layer formation process. This preliminary action prevents damage to the active region and provides a stress-free base layer for subsequent polysilicon growth, ensuring both good crystalline characteristics and stable driving currents.
Solution Approach 2:
The amorphous silicon layer serves as an intermediary layer between the substrate and the polysilicon layer. It protects the active region from damage during processing and eliminates interface stress that would otherwise be generated in multilayer structures, thereby improving the crystalline quality of the polysilicon layer.
2Manufacturing precision
If a high temperature heat treatment process is used to crystallize the amorphous silicon layer, then the polysilicon layer can be formed, but the thermal budget is high and leakage currents increase
Solution Approach 1:
The crystallization process is performed at a relatively low temperature (below 400°C) compared to conventional high-temperature processes. This parameter change in temperature reduces the thermal budget and energy consumption while still achieving complete crystallization of the amorphous silicon layer to form high-quality polysilicon with stable electrical characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures stable driving currents and reduces defects and leakage currents in the polysilicon layer, improving the crystalline characteristics and operational efficiency of the semiconductor device.
Implementation Method 1
crystallizing the amorphous silicon layer using the metal silicide layer to form a polysilicon layer
Implementation Method 2
forming an amorphous silicon layer using a CVD process
Data Source
AI summary
A method of forming a vertical diode and a method of manufacturing a semiconductor device (e.g., a semiconductor memory device such as a phase-change memory device) includes forming an insulating structure having an opening on a substrate and filling the opening with an amorphous silicon layer. A metal silicide layer is formed to contact at least a portion of the amorphous silicon layer and a polysilicon layer is then formed in the opening by crystallizing the amorphous silicon layer using the metal silicide layer. A doped polysilicon layer is formed by implanting impurities into the polysilicon layer. Thus, the polysilicon layer is formed in the opening without performing a selective epitaxial growth (SEG) process, so that electrical characteristics of the diode may be improved.