Vertical Double-Gate Semiconductor Structure for Leakage Control
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Solution Overview
Problem
The increasing integration density of dynamic memory in semiconductor structures poses challenges in controlling potential leakage between small-sized functional devices, requiring improved electrical performance and anti-leakage performance.
Innovation Solution
A semiconductor structure with a double-gate configuration, where a first and second gate layer surround vertical transistor structures, complementing each other's control capabilities, and extending to a peripheral region with an electrical connection structure to diversify potential control and reduce leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vertical gate-all-around (GAA) transistors are used to increase integration density, then the area occupied by transistors is reduced, but leakage current increases and control performance deteriorates
Solution Approach 1:
The gate structure is segmented into multiple separate gate layers (first gate layer and second gate layer) that are spatially distributed around the vertical transistor. Each gate layer can be independently controlled and optimized, allowing better control over the transistor channel while maintaining high integration density. The segmentation enables differentiated control strategies for different regions of the gate structure.
Solution Approach 2:
The patent transitions from a single-plane gate structure to a three-dimensional multi-layer gate arrangement surrounding the vertical transistor. The first and second gate layers are positioned at different vertical levels and radial positions, creating a multi-dimensional control architecture that enhances control capability without increasing the planar footprint, thus maintaining high integration density.
2Productivity
If transistor size is reduced to increase integration density, then more transistors fit in the same area, but anti-leakage performance deteriorates
Solution Approach 1:
The gate layers are nested around the vertical transistor structure in concentric circular arrangements. The first gate layer and second gate layer are positioned at different radial distances from the transistor channel, creating a nested configuration where each gate layer can independently control the channel while the overall structure remains compact. This nesting enables effective leakage control in small-sized transistors without increasing the overall device footprint.
3Reliability
If multiple gate layers are added to improve control performance, then leakage current is reduced, but device complexity increases
Solution Approach 1:
Multiple gate layers are merged into a unified control system where the first gate layer and second gate layer work cooperatively to control the vertical transistor. The gate layers are electrically connected through contact holes that allow signal transmission between different gate layers and to external control circuits. This merging approach enables enhanced control performance while managing complexity through integrated design and shared control logic.
Data Source
AI summary
The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base, where the base is provided with an array region and a peripheral region, the array region is provided with vertical transistor structures, the vertical transistor structures are arranged in an array in the array region, and the peripheral region surrounds the array region; a first gate layer surrounding the vertical transistor structure and extending along a first direction; a second gate layer surrounding the vertical transistor structure and extending along the first direction, where the second gate layer and the first gate layer surround a same vertical transistor structure, are disposed at intervals, and both extend to the peripheral region; and an electrical connection structure located in the peripheral region and electrically connected to the first gate layer and the second gate layer.