Vertical Double-Gate OTFT Structure for High Aperture Ratio
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Solution Overview
Problem
The existing double-bottom-gate oxide thin film transistors (OTFTs) occupy a large area in the pixel region, which reduces the aperture ratio and light transmittance of array substrates used in LCD and AMOLED displays.
Innovation Solution
A method of manufacturing a double-gate OTFT with a vertical structure, where two transistors share the same source/drain metal layer, with the metal layer functioning as both source and drain in different transistors, and the gate and source/drain electrodes are arranged vertically, reducing the overall area occupied by the transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a double-bottom-gate structure is used to control grey scales in pixel regions, then the transistor can effectively control liquid crystal rotation or electroluminescent brightness, but the transistor occupies a large area which reduces the aperture ratio and light transmittance
Solution Approach 1:
The patent transitions from a planar double-bottom-gate structure to a vertical stacked structure where the gate electrode is positioned above the semiconductor layer rather than beneath it. This dimensional change allows the transistor components to be arranged in the vertical direction (z-axis) instead of spreading out in the horizontal plane, thereby reducing the area occupied by the transistor while maintaining its control functionality for grey scale regulation in LCD or AMOLED displays
2Area of stationary object
If the double-gate width is minimized to reduce area, then the aperture ratio improves, but the manufacturing precision and structural stability become more challenging
Solution Approach 1:
The patent segments the transistor structure into distinct vertical layers: substrate, buffer layer, semiconductor layer, gate insulating layer, and gate electrode. Each layer is formed through separate deposition and etching processes, allowing for independent optimization of each component's dimensions and properties. This segmentation enables precise control of the gate width and alignment without compromising manufacturing feasibility
Solution Approach 2:
The patent combines multiple functional layers into a unified vertical stack where the gate electrode, gate insulating layer, and semiconductor layer are integrated in the vertical direction. This merging approach consolidates what would traditionally be separate planar components into a compact vertical assembly, reducing overall transistor area while maintaining structural integrity through the stacked configuration
Data Source
AI summary
Embodiments of the present invention provide a method for manufacturing a transistor, a transistor, an array substrate and a display device. The method comprises: forming a first source/drain metal layer on a substrate; forming an insulating layer above the first source/drain metal layer; forming a gate metal layer on the insulating layer; forming a gate insulating layer on the gate metal layer; forming a semiconductor layer above the gate insulating layer; forming an etching blocking layer on the semiconductor layer; forming a second source/drain metal layer above the etching blocking layer; forming an insulating layer above the second source/drain metal layer.