Vertical-Channel DRAM Cell Array With 2D Word Lines for Lower RC Delay
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current dynamic random-access memory (DRAM) devices face challenges in reducing the area of each unit device while maintaining efficient transistor performance, as existing vertical-channel cell array transistor structures do not effectively utilize two-dimensional materials to enhance transistor density and reduce resistive-capacitive delay.
Innovation Solution
The implementation of a vertical-channel cell array transistor structure that includes a semiconductor substrate with perpendicularly arranged channels, a gate insulating layer, word lines extending in a specific direction, and a two-dimensional material layer on the word lines' surfaces, which can be conductors, insulators, or semiconductors, such as graphene or transition metal dichalcogenides, to reduce resistance and prevent damage during ion implantation processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar transistor structures are used, then manufacturing is simpler, but device area is larger and transistor density is lower
Solution Approach 1:
The patent transitions from planar (2D) transistor channels to vertical (3D) channels extending perpendicular to the substrate surface. This dimensional change allows multiple channels to be packed within the same footprint area, significantly increasing transistor density without proportionally increasing the device area. The vertical channel structure enables higher integration while maintaining manufacturability through established semiconductor fabrication processes.
2Speed
If word lines are made with conventional materials, then manufacturing is easier, but resistance is higher causing increased RC delay
Solution Approach 1:
The patent employs composite material structures for word lines, combining multiple materials with complementary properties. This includes using low-resistance materials such as copper or cobalt in conjunction with barrier layers and adhesion layers. The composite structure reduces overall resistance and RC delay while remaining compatible with existing semiconductor manufacturing processes, achieving both performance improvement and manufacturability.
3Reliability
If ion implantation is performed without protective layers, then processing is simpler, but surface damage and oxidation occur
Solution Approach 1:
The patent applies protective layers (such as nitrogen-containing dielectric layers or oxide layers) to the substrate surface and channel regions before performing ion implantation. This preliminary protective action prevents surface damage and oxidation during the ion implantation process, ensuring surface integrity and device reliability. The protective layers are subsequently removed or integrated into the final device structure, adding minimal complexity while significantly improving reliability.
4Area of stationary object
If unit device area is reduced for higher integration, then device density increases, but transistor performance may deteriorate
Solution Approach 1:
The patent uses vertical channel structures that extend perpendicular to the substrate, allowing the channel length to be controlled independently of the device footprint. This enables reduction of the planar device area while maintaining adequate channel length for proper transistor performance. The vertical configuration decouples the area scaling from performance degradation, enabling high-density integration without sacrificing transistor characteristics.
Solution Approach 2:
The patent implements localized doping regions, gate structures, and material compositions tailored to specific areas of the vertical channel device. By optimizing the local properties of different regions (such as doping concentrations in source/drain regions, gate dielectric thickness, and material composition), the transistor performance is maintained or enhanced even as the overall device area is reduced for higher integration density.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
Provided are a vertical-channel cell array transistor structure (100) and a dynamic random-access memory (DRAM) device including the same. The vertical-channel cell array transistor structure includes a semiconductor substrate (110), a plurality of channels (140) arranged in an array on the semiconductor substrate and each extending perpendicularly from the semiconductor substrate, a gate insulating layer (130) on the plurality of channels, a plurality of word lines (150) on the semiconductor substrate and extending in a first direction, and a two-dimensional (2D) material layer (190) on at least one surface of each of the plurality of word lines.