Vertical DRAM Transistor Air-Gap Structure for Lower Word Line Capacitance
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Solution Overview
Problem
DRAM manufacturers face challenges in shrinking memory cell area due to increasing parasitic capacitance and word line resistance as word line spacing decreases.
Innovation Solution
The semiconductor device incorporates a novel structure with first and second vertical transistors, each with a word line wrapping the channel region and a dielectric layer between the channel and word line. An air gap is inserted between the transistors, sealed by dielectric layers, to reduce parasitic capacitance and word line resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If word line spacing is decreased to shrink memory cell area, then memory cell area is reduced, but parasitic capacitance between word lines increases
Solution Approach 1:
The patent extracts the problematic dielectric material between adjacent word lines by creating air gaps. The air gap structure removes the dielectric substance that causes parasitic capacitance, directly addressing the harmful factor while allowing reduced word line spacing for smaller memory cell area.
Solution Approach 2:
The patent changes the dielectric parameter between word lines from a solid dielectric material to an air gap (effectively changing the dielectric constant). This parameter change reduces the parasitic capacitance between closely spaced word lines, enabling further area reduction without suffering from capacitance penalties.
2Area of stationary object
If word line spacing is decreased to shrink memory cell area, then memory cell area is reduced, but word line resistance increases
Solution Approach 1:
The patent transitions from planar word line structures to three-dimensional wrapped word line structures that encircle the channel region. This dimensional change allows the word line to be closer to the channel (improving coupling) while the air gap prevents resistance increase by maintaining proper spacing and reducing capacitive loading that would slow signal propagation.
Solution Approach 2:
The air gap acts as an intermediary structure that mediates between the need for close word-line-to-channel spacing (for good coupling in small cells) and the need to minimize word line resistance. The air gap reduces capacitive coupling to adjacent word lines, preventing signal interference and resistance increase.
3Productivity
If vertical transistors are placed adjacent to each other, then device density is improved, but parasitic capacitance between adjacent structures increases
Solution Approach 1:
The patent extracts the dielectric material between adjacent vertical transistor structures, creating air gaps between them. This removal of dielectric substance directly reduces parasitic capacitance between densely packed transistors, enabling higher device density without capacitance penalties.
Solution Approach 2:
The air gap structure applies local quality changes by creating non-uniform spacing between adjacent vertical transistors. The gaps are strategically positioned between closely spaced structures where parasitic capacitance would be highest, while maintaining proper spacing and electrical isolation where needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces parasitic capacitance and word line resistance, allowing for a smaller memory cell area while maintaining device performance.
Implementation Method 1
a parasitic capacitance between the word lines may be a problem as the spacing between two closely arranged word lines continues to shrink. Accordingly, there is a demand for a novel structure for reducing the parasitic capacitance and word line resistance.
Implementation Method 2
The first vertical transistor includes a first channel region, a first word line wrapping the first channel region, and a first word line dielectric layer between the first channel region and the first word line.
Data Source
AI summary
A semiconductor device includes a first vertical transistor and a second vertical transistor adjacent to the first vertical transistor. The first vertical transistor includes a first channel region, a first word line wrapping the first channel region, and a first word line dielectric layer between the first channel region and the first word line. The second vertical transistor includes a second channel region, a second word line wrapping the second channel region, and a second word line dielectric layer between the second channel region and the second word line. The semiconductor device further includes a dielectric layer wrapping upper portions of the first word line and the second word line, and an air gap inserted between lower portions of the first vertical transistor and the second vertical transistor.