Vertical Oxide Semiconductor DRAM Cell for Low Bit Line Capacitance
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Solution Overview
Problem
Conventional DRAM technologies face issues with parasitic BL junction capacitance and high bit line capacitance, which affect signal propagation and data retention in 3D ICs, particularly in small footprint 4F2 DRAM structures.
Innovation Solution
The proposed method involves forming a 3D memory cell structure with metal bit lines and using plasma-enhanced oxidation to improve gate oxide quality, creating an air gap between bit lines to reduce parasitic capacitance and impedance, and employing a vertical access transistor with a buried bit line to minimize series resistance and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional DRAM structures are used with small footprint 4F2 design, then area is reduced, but parasitic BL junction capacitance and bit line capacitance increase
Solution Approach 1:
The patent transitions from planar bit line structures to vertical 3D IC structures. Bit lines are formed as vertical conductors extending through multiple layers, and memory cells are stacked in the vertical dimension. This dimensional change allows reduced footprint area while minimizing parasitic capacitance by separating bit lines from junctions in the vertical direction rather than confining them in the same plane.
Solution Approach 2:
The bit line structure is segmented into multiple vertical segments across different layers. Each bit line is divided into portions at different vertical levels, allowing isolation of capacitive effects. The junctions are also segmented and positioned at different vertical locations from the bit lines, reducing the overlap and thus parasitic capacitance.
2Reliability
If vertical access transistor with buried bit line is used, then series resistance and capacitance are reduced, but device complexity increases
Solution Approach 1:
The vertical access transistor structure embeds the bit line within the transistor architecture. The bit line is positioned as a buried conductor within or alongside the vertical channel structure, nesting multiple functional elements (bit line, channel, gate, junction) in a compact vertical arrangement. This nesting reduces the number of external connections and minimizes series resistance and capacitance while maintaining functionality.
Solution Approach 2:
The bit line is formed as a buried structure before the final transistor components are completed. This preliminary formation of the bit line conductor allows subsequent layers to be built around it, optimizing the electrical path and minimizing resistance and capacitance before the full device complexity is introduced.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces parasitic capacitance and series resistance, enhancing signal propagation and data retention in 3D ICs by eliminating parasitic junction capacitance and bit line capacitance, thereby improving the overall performance of 4F2 DRAM cells.
Implementation Method 1
using plasma-enhanced oxidation to improve gate oxide quality
Implementation Method 2
creating an air gap between bit lines to reduce parasitic capacitance and impedance
Data Source
AI summary
A method of making a semiconductor device that includes forming a vertical access transistor including forming bit lines in a first direction on a substrate, forming a polysilicon pillar as a sacrificial pillar over each bit line of the bit lines, forming a gate oxide on side surfaces of the polysilicon pillar, forming a word line, in a second direction, on the polysilicon pillar with the gate oxide interposed between the word line and the polysilicon pillar, the second direction being not substantially parallel to the first direction, after forming the word line, removing the polysilicon pillar so as to leave a vertical void in place of the polysilicon pillar, filling the vertical void with an oxide semiconductor that serves as a channel for the vertical access transistor; and forming a cell capacitor over the channel of the vertical access transistor.