Vertical DRAM Transistor Structure With Surrounding Bit Line Contact
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Solution Overview
Problem
The use of vertical gate-all-around transistors in DRAMs leads to excessively large contact resistance between metal and semiconductor materials due to Schottky barriers and metal-induced gap states, affecting the output current and electrical performance.
Innovation Solution
A semiconductor structure is fabricated with a columnar structure including a source, conductive channel, and drain, surrounded by a bit line trench, and a gate-all-around word line with air gaps, using materials like molybdenum disulfide and bismuth metal to reduce contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If vertical gate-all-around transistor is used to reduce feature size, then device miniaturization is achieved, but contact resistance between metal and semiconductor material increases excessively
Solution Approach 1:
The patent transitions from planar contact geometry to three-dimensional surrounding contact geometry. The bit line is configured to surround the source region in a U-shape or C-shape configuration, increasing the contact area from a single point or line to a multi-faceted surface contact. This dimensional change in contact geometry reduces contact resistance while maintaining the vertical gate-all-around transistor's miniaturized footprint.
Solution Approach 2:
The contact structure is segmented into multiple contact regions between the bit line and source region. Instead of a single large contact, the surrounding configuration creates multiple discrete contact points or regions distributed around the source, which reduces the current density at each individual contact point and lowers overall contact resistance.
2Volume of moving object
If channel width is continuously reduced, then transistor size is minimized, but output current fails to meet operation requirements
Solution Approach 1:
The invention moves the contact improvement strategy from the horizontal plane to the vertical dimension. By implementing surrounding contacts that wrap around the source region vertically and horizontally, the effective contact area increases significantly without increasing the transistor's planar footprint. This enables maintained or improved output current in miniaturized transistors.
Solution Approach 2:
The patent employs composite material structures in the contact regions, combining metal materials with specific semiconductor materials to optimize electrical properties. The bit line and source region use carefully selected material combinations that reduce Schottky barrier effects and improve carrier injection, enabling high output current in small transistors.
Data Source
AI summary
This invention relates to a semiconductor structure and a fabrication method therefor. The method for fabricating a semiconductor structure includes: providing a substrate, where a shallow trench isolation structure is formed on the substrate; forming a plurality of transistor accommodating grooves in the active regions, where there is a spacing between the transistor accommodating groove and the shallow trench isolation structure; forming a columnar structure in the transistor accommodating groove, where the columnar structure includes a source, a conductive channel, and a drain that are sequentially disposed in a direction away from the substrate; etching the active region located within the spacing and the active region located between adjacent columnar structures in the same active region to form a bit line trench, where the bit line trench surrounds the source; and forming a bit line that surrounds and connects the source in the bit line trench.