Vertical Channel DRAM Layout With Lower Bit Line and Peripheral Gate
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Solution Overview
Problem
As semiconductor devices shrink in size, it becomes challenging to maintain the desired performance of transistors, particularly in dynamic random-access memory (DRAM), where forming reliable and stable elements with reduced sizes is difficult.
Innovation Solution
The semiconductor device incorporates a vertical channel transistor with a vertical channel region and a peripheral gate, where the bit line is electrically connected at a lower level than the transistor, and the peripheral gate is disposed at the same level as the bit line, enhancing integration density and electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If element sizes are reduced to increase integration density, then integration density is improved, but transistor performance deteriorates
Solution Approach 1:
The patent transitions from planar transistor architecture to a vertical channel architecture where the channel extends in the vertical direction rather than horizontally. This dimensional change allows the transistor to maintain adequate channel length and surface area for performance while reducing the horizontal footprint, thereby increasing integration density without sacrificing transistor performance
Solution Approach 2:
The patent implements a three-dimensional structure where the bit line is positioned below the vertical channel transistor, and the peripheral gate is disposed at the same level as the bit line. This nested arrangement allows multiple components to occupy different vertical levels within a compact horizontal space, increasing integration density while maintaining proper electrical connections and transistor performance
2Area of moving object
If element sizes are reduced, then integration density is improved, but manufacturing stability deteriorates
Solution Approach 1:
By moving to vertical channel architecture, the patent reduces sensitivity to lateral dimensional variations. The vertical channel structure provides more stable electrical characteristics because the channel length is defined by vertical etching depth rather than lateral lithography dimensions, which are more prone to variability at scaled dimensions
Solution Approach 2:
The patent separates the bit line and peripheral gate into distinct vertical levels, with the bit line positioned below the vertical channel transistor and the peripheral gate at the same level as the bit line. This segmentation allows independent optimization and manufacturing control of each component, improving overall manufacturing stability
Data Source
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Figure 2A
AI summary
A semiconductor device includes a vertical channel transistor including a vertical channel region extending in a vertical direction and a cell gate electrode facing a first side surface of the vertical channel region. A bit line is electrically connected to the vertical channel transistor at a level that is lower than a level of the vertical channel transistor. A peripheral semiconductor body has at least a portion thereof disposed on a same level as the vertical channel region. Peripheral source/drain regions are disposed in the peripheral semiconductor body and are spaced apart from each other in a horizontal direction. A peripheral channel region is disposed between the peripheral source/drain regions in the peripheral semiconductor body. A peripheral gate is disposed below the peripheral semiconductor body. At least a portion of the peripheral gate is disposed on a same level as at least a portion of the bit line.