Vertical DRAM Capacitor with Insulating Division Layer
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Solution Overview
Problem
The miniaturization of DRAM devices has led to challenges in forming well-defined electrodes and dielectric layers within capacitors due to space constraints, resulting in potential capacitor deterioration.
Innovation Solution
A semiconductor device design featuring first and second electrodes with a dielectric layer on their sidewalls, separated by an insulating division layer, which are formed using a single process to enhance process margin and fabrication efficiency, with the electrodes extending vertically and alternating horizontally, and contact plugs connecting to these electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If capacitor size is decreased to accommodate miniaturized DRAM devices, then device integration density is improved, but electrode and dielectric layer formation quality deteriorates due to space constraints
Solution Approach 1:
The patent transitions from planar capacitor structures to vertically stacked capacitor structures with multiple electrodes and dielectric layers arranged in the vertical dimension. This allows increased capacitance density without increasing the horizontal footprint, effectively resolving the contradiction between miniaturization and formation quality by utilizing the third dimension for structural complexity.
Solution Approach 2:
The patent implements nested capacitor structures where multiple electrodes and dielectric layers are stacked within each other vertically. The first electrode, second electrode, and additional electrodes are nested with corresponding dielectric layers between them, creating a compact multi-layer capacitor structure that maintains high formation quality while minimizing area occupation.
2Manufacturing precision
If multiple electrodes and dielectric layers are formed using separate processes, then manufacturing precision is improved, but fabrication complexity and time increase
Solution Approach 1:
The patent combines the formation of multiple electrodes and dielectric layers into a single integrated process step. The first electrode, second electrode, and additional electrodes along with their corresponding dielectric layers are formed simultaneously rather than through separate sequential processes, thereby improving fabrication efficiency while maintaining manufacturing precision through the unified process approach.
Solution Approach 2:
The single process used to form multiple electrodes and dielectric layers serves multiple functions simultaneously: it creates conductive paths, forms insulating barriers, and establishes the capacitive structure all in one operation. This multi-functional process approach resolves the contradiction by achieving what would traditionally require multiple specialized processes.
3Quantity of substance
If dielectric layer thickness is reduced to increase capacitance density, then capacitance is improved, but leakage current increases
Solution Approach 1:
The patent employs composite dielectric structures with multiple dielectric layers having different material compositions and properties. The first dielectric layer, second dielectric layer, and additional dielectric layers are formed with varying thicknesses and materials to optimize the balance between capacitance density and leakage current suppression, resolving the contradiction through material composition diversity rather than uniform thinning.
Solution Approach 2:
The patent segments the dielectric structure into multiple distinct dielectric layers rather than using a single thick or thin layer. Each dielectric layer can be independently optimized for specific functions: some layers provide high capacitance while others provide low leakage paths. This segmentation allows the system to achieve high capacitance density without suffering from the leakage issues that would result from uniformly reducing dielectric thickness.
Data Source
AI summary
A semiconductor device includes a first contact plug on a substrate, a capacitor, an insulating division layer, and a second contact plug. The capacitor includes first and second electrodes and a dielectric layer. The first electrode contacts an upper surface of the first contact plug, and extends in a vertical direction substantially perpendicular to an upper surface of the substrate. The second electrode is spaced apart from the first electrode, and extends in the vertical direction and includes lower and upper surfaces substantially coplanar with lower and upper surfaces, respectively, of the first electrode. The dielectric layer is on sidewalls of the first and second electrodes. The insulating division layer is formed between portions of the dielectric layer on the sidewalls of the first and second electrodes. The second contact plug contacts the upper surface of the second electrode.