Vertical DRAM Capacitor Stack for Higher Density Memory Cells
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Solution Overview
Problem
The fabrication of capacitors in dynamic random access memory (DRAM) with reduced size and increased layers is challenging, leading to difficulties in improving capacitor capacity and affecting storage performance.
Innovation Solution
A semiconductor device with a stack structure comprising alternately stacked conductive and dielectric layers, including a vertical transistor connected through a connection structure, allows for the formation of planar capacitors with adjustable capacity and improved memory density through an nTnC design, where each memory cell includes multiple transistors and capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of the capacitor is reduced and the number of layers in a stack is increased, then the memory density is improved, but the fabrication difficulty increases
Solution Approach 1:
The patent transitions from planar capacitor fabrication to vertical stack architecture, utilizing the third dimension (vertical direction) to increase memory density. The stack structure comprises multiple conductive layers and dielectric layers stacked vertically, allowing capacitors to be formed in three-dimensional space rather than confined to a two-dimensional plane, thereby achieving higher density without proportionally increasing fabrication complexity
Solution Approach 2:
The capacitor structure is segmented into multiple discrete conductive layers (first conductive layers and second conductive layers) separated by dielectric layers. This segmentation allows for modular fabrication where each layer can be formed and connected through vertical connection structures, enabling systematic manufacturing of high-density stacks through repeated patterning and deposition cycles
2Quantity of substance
If the capacitor size is reduced, then the memory density is improved, but the capacitor capacity deteriorates
Solution Approach 1:
The patent compensates for reduced individual capacitor capacity by stacking multiple capacitors vertically. The total capacitance is distributed across multiple layers in the vertical dimension, where each layer contributes to the overall storage capacity. This allows the device to maintain adequate total capacity while achieving higher density through vertical integration rather than lateral expansion
Solution Approach 2:
Multiple capacitors are merged into a single vertical stack structure, where the cumulative effect of multiple capacitor layers provides sufficient total capacity. The stack structure combines multiple first conductive layers, second conductive layers, and dielectric layers into an integrated unit that functions as a high-density capacitor array, merging the functionality of multiple discrete capacitors into one compact vertical structure
Data Source
AI summary
Semiconductor devices, methods for forming such semiconductor devices, and systems including such semiconductor devices are provided. In one aspect, a semiconductor device includes a first semiconductor structure that includes a stack structure and a transistor. The stack structure includes first conductive layers and second conductive layers that are stacked alternately in a first direction. The transistor is disposed on one side of the stack structure and connected with one of the first conductive layers. The first semiconductor structure further includes a first connection structure extending through the stack structure in the first direction and connected to the second conductive layers.