Vertical DRAM Cell Structure for Higher Density With Lower Leakage
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Solution Overview
Problem
Increasing memory capacity in semiconductor devices, such as dynamic random access memory (DRAM), is challenging due to limitations in reducing the machining dimension, which hinders the miniaturization of memory cells.
Innovation Solution
A vertical structure is implemented for both the access transistor and storage capacitor of the memory cell, reducing the planar area and enhancing memory capacity through specific layering and bonding techniques, including epitaxial growth, anisotropic etching, and wafer bonding, allowing for the formation of vertically stacked transistors and capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the machining dimension is reduced to increase memory capacity, then the memory capacity increases, but the machining precision and manufacturing difficulty worsen
Solution Approach 1:
The patent transitions from planar (2D) memory cell layout to vertical (3D) stacking architecture. Memory cells are arranged in multiple layers stacked vertically, with through-silicon vias (TSVs) enabling inter-layer connections. This dimensional change allows significant increase in memory capacity without further reducing the lateral machining dimension, thereby avoiding the associated manufacturing precision challenges.
2Productivity
If the planar area of memory cell is reduced to increase integration density, then the integration density increases, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The memory device is segmented into multiple functional layers stacked vertically, including memory cell layers, cache layers, and interconnect layers. Each layer can be independently designed and manufactured, then bonded together. This segmentation allows complex functionality to be achieved through modular assembly rather than complex planar integration, managing device complexity while achieving high integration density.
Solution Approach 2:
The patent implements a nested vertical structure where smaller functional units are stacked within larger structural frameworks. Memory cells are nested within vertical columns, which are nested within larger memory arrays. This nested architecture achieves high integration density by efficiently utilizing the vertical space without proportionally increasing manufacturing complexity.
3Area of stationary object
If vertical stacking is implemented to reduce planar area, then the planar area is reduced, but the leakage current and positional displacement increase
Solution Approach 1:
The patent introduces intermediary structures between stacked layers, including insulating layers between conductive layers, barrier layers in TSVs, and isolation structures between vertical columns. These intermediary elements electrically isolate adjacent components, preventing leakage current paths while maintaining the compact vertical architecture. The intermediary layers act as mediators that enable close proximity stacking without compromising electrical isolation and reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the planar area occupied by memory cells, enabling higher integration density and cost-effective semiconductor devices with improved yield by minimizing leakage current and positional displacement.
Implementation Method 1
a first semiconductor layer, a second semiconductor layer, and a first insulating material layer are formed in a stacked manner on a first semiconductor substrate
Implementation Method 2
a second insulating material layer and shield plates are formed in the gaps between the island-shaped structures
Implementation Method 3
the first member is bonded to the second member and the third member in a stacked manner by a wafer bonding technique
Data Source
AI summary
An apparatus includes a semiconductor substrate; an access transistor including channel, source and drain regions arranged in a vertical direction to the semiconductor substrate and a gate-electrode facing to the channel region; a storage capacitor coupled to one of the source and drain regions; a bit-line coupled to the other of the source and drain regions; and a pull-out-electrode connected to the bit-line; wherein surfaces of the source and drain regions and the pull-out-electrode on the bit-line side is arranged at substantially the same height from the upper surface of the semiconductor substrate.