Vertical DRAM Cell Structure for High Data Transfer Rate
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Solution Overview
Problem
The challenge is to enhance the data transfer rate between logic circuits and DRAMs, as the DRAM technology lags behind logic circuit advancements, leading to issues like increased interfaces, power dissipation, and noise, due to slower scaling of DRAM processing nodes compared to logic circuit technology.
Innovation Solution
A DRAM cell structure with vertically oriented conductive regions, a gate structure, and a capacitor design that includes an insulating layer and electrodes, allowing for compact self-aligned construction and efficient interconnections, thereby facilitating faster data migration and reducing migration costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If DRAM processing node scaling continues at current pace, then device complexity and interface requirements increase, but data transfer rate and bandwidth cannot keep up with logic circuit demands
Solution Approach 1:
The patent transitions from planar 2D capacitor structures to three-dimensional vertically stacked capacitor structures. The capacitor electrodes are arranged in multiple tiers above the substrate, with insulating layers between them, creating a vertical stacking configuration that increases storage density without expanding the lateral footprint. This dimensional change enables higher data transfer rates and bandwidth while maintaining compact device geometry and reducing interface complexity.
2Productivity
If DRAM processing node scaling continues at current pace, then power dissipation and thermal management become more difficult, but data transfer bandwidth remains insufficient
Solution Approach 1:
By stacking capacitor electrodes vertically in multiple tiers with insulating layers between them, the patent increases storage density and bandwidth without increasing the lateral device footprint. This vertical integration reduces the number of interconnect layers and interfaces required, thereby reducing power dissipation and thermal management complexity while achieving higher data transfer bandwidth.
3Productivity
If DRAM processing node scaling continues at current pace, then noise and signal integrity issues increase, but data transfer rate cannot match logic circuit speed
Solution Approach 1:
The vertically stacked capacitor structure with multiple tiers of electrodes and insulating layers increases storage density and data transfer rate while maintaining a compact lateral footprint. This vertical integration reduces the number of interconnect layers and interfaces, thereby reducing noise and signal integrity issues associated with longer signal paths and more interfaces, enabling data transfer rates to match logic circuit speed.
Data Source
AI summary
This invention discloses a DRAM cell includes an asymmetric transistor coupled to a capacitor. The asymmetric transistor includes a drain region extending upward from an isolator region; a gate region extends upward from a gate dielectric or the isolator; a source region of asymmetric transistor extends upward from a first portion of an isolating layer. The upward extending directions of the drain region, the gate region, and the source region are perpendicular or substantially perpendicular to an original silicon surface. Moreover, the capacitor is partially formed in a concave and the isolating layer is positioned in the concave. The capacitor extends upward from a second portion of the isolating layer. The upward extending directions of the upright portion of the capacitor electrode, the third portion of the insulating layer and the counter electrode are perpendicular or substantially perpendicular to the original silicon surface.