Vertical DRAM Pillar Layout With Direct Bit Line Connection
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Solution Overview
Problem
The manufacturing process of DRAM is complicated, and the signal interconnection paths are long, limiting storage capacity and integration.
Innovation Solution
A semiconductor structure with a vertical transistor layout where the bit line is directly formed on the top portion of an active pillar, reducing the need for additional contacts and interconnection lines, and allowing for a Chip On Wafer process, thereby simplifying the process and improving space utilization and signal transmission speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional DRAM structure with separate contacts and interconnection lines is used, then the manufacturing process is complex and signal interconnection paths are long, but the storage capacity and integration can be improved
Solution Approach 1:
The patent merges the bit line directly with the active pillar top portion, eliminating the need for separate contacts and interconnection lines. This integration reduces manufacturing process complexity while enabling higher storage capacity and integration by allowing closer spacing of memory cells.
Solution Approach 2:
The patent transitions from a planar layout to a vertical architecture where the bit line extends in the vertical dimension to directly contact the active pillar. This dimensional change shortens signal paths and reduces the number of interconnection layers needed, improving both manufacturing simplicity and integration density.
2Device complexity
If additional contacts and interconnection lines are used, then the manufacturing process becomes more complex, but the signal transmission path is longer
Solution Approach 1:
The patent extracts and eliminates unnecessary intermediate contacts and interconnection lines from the signal path. By directly forming the bit line on the active pillar top portion, it removes redundant components that both complicate manufacturing and extend signal transmission paths, thereby improving signal speed.
3Device complexity
If the bit line is directly formed on the top portion of the active pillar, then the number of contacts and interconnection lines is reduced, but the thermal resistance increases
Solution Approach 1:
The vertical formation of the bit line on the active pillar top portion creates direct thermal conduction paths through the vertical structure. This dimensional arrangement improves heat dissipation by providing direct thermal coupling between the active region and the bit line, reducing thermal resistance despite the reduced number of contacts.
Data Source
Figure 1~2b
Figure 3~4b
Figure 4c~4e
AI summary
An embodiment of the application provides a semiconductor structure. The semiconductor structure includes: a substrate; a plurality of capacitors arranged in the substrate; and a plurality of active pillars arranged above the substrate. Each of the plurality of active pillars is arranged above a respective one of the plurality of capacitors, and a bottom portion of each of the plurality of active pillars is electrically connected to a top portion of the respective one of the plurality of capacitors therebelow.