Vertical 1T DRAM Cell Structure for Floating-Body Noise Suppression
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Capacitorless single-transistor DRAM memory devices experience strong capacitive coupling between the word line and the floating body, leading to noise transmission during data reading and writing, resulting in erroneous data reading and writing, and lack sufficient margin for potential differences between written states, hindering practical use and density increase.
Innovation Solution
A memory device structure featuring a first and second semiconductor base material with different impurity concentrations, surrounded by gate insulating and conductor layers, where voltage control across impurity and gate conductor layers performs write, read, and erase operations, optimizing gate capacitances to reduce noise influence and enhance operational margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If capacitorless single-transistor DRAM is used to increase integration density, then device complexity is reduced, but strong capacitive coupling between word line and floating body causes noise transmission during read/write operations
Solution Approach 1:
The patent introduces a plate line as an intermediary element that couples to the floating body through a plate capacitance. This plate line acts as a mediator to provide an additional charge storage path, reducing the direct capacitive coupling between the word line and floating body. By adding this intermediary structure, the noise transmission from word line oscillations is suppressed while maintaining the capacitorless single-transistor configuration.
Solution Approach 2:
The patent modifies the electrical parameters of the memory cell by introducing a plate line with specific capacitance characteristics. The plate capacitance is designed to be comparable to or larger than the word line capacitance, changing the charge distribution parameters and reducing the voltage oscillation amplitude on the floating body during read/write operations.
2Speed
If strong capacitive coupling exists between word line and floating body, then write operation speed is improved, but operational margin for potential differences between written states becomes insufficient
Solution Approach 1:
The plate line serves as an intermediary charge storage element that decouples the strong direct capacitance between word line and floating body. This allows the write operation to proceed through the plate line interface, maintaining speed while reducing the harmful direct coupling that limits operational margin.
Solution Approach 2:
The patent segments the charge storage function by separating it into two components: the word line capacitance for fast write operations and the plate line capacitance for stable charge storage. This segmentation allows each component to optimize its function, with the plate line providing the additional margin needed for reliable read operations.
3Device complexity
If floating body is directly coupled to word line, then device structure is simplified, but noise from word line voltage oscillation directly affects reading and writing accuracy
Solution Approach 1:
The plate line is introduced as an intermediary element between the word line and floating body, providing an additional charge storage path that reduces the direct capacitive coupling. This intermediary structure suppresses the transmission of voltage oscillation noise from the word line to the floating body, improving read/write accuracy while maintaining the simplified capacitorless single-transistor configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure effectively suppresses voltage oscillation noise, increasing the operational margin and enabling higher density and reliability of dynamic flash memory cells by controlling voltage across distinct semiconductor regions.
Implementation Method 1
a first gate insulating layer partially or entirely surrounding a side face of the first semiconductor base material on one end side; a second gate insulating layer continuous with the first gate insulating layer, and partially or entirely surrounding a side face of the second semiconductor base material on another end side; a first gate conductor layer covering the first gate insulating layer; a second gate conductor layer covering the second gate insulating layer
Implementation Method 2
a first impurity layer provided on an outer side of one end of the first gate conductor layer along a direction of extension of the first semiconductor base material, the first impurity layer having a polarity opposite to a polarity of the first semiconductor base material; and a second impurity layer provided on an outer side of one end of the second gate conductor layer, the second impurity layer having a polarity opposite to a polarity of the second semiconductor base material
Implementation Method 3
When the MOS transistor 110a is operated in the saturation region... accelerated electrons flowing from the source N+ layer 103 to the drain N+ layer 104 collide with Si lattices, and electron-hole pairs are generated due to the kinetic energy lost during the collision (i.e., an impact ionization phenomenon)
Data Source
AI summary
Provided on a substrate 1 are an N+ layer connecting to a source line SL, a first Si pillar as a P+ layer standing in an upright position along the vertical direction, and a second Si pillar as a P layer. An N+ layer connecting to a bit line BL is provided on the second Si pillar. A first gate insulating layer is provided so as to surround the first Si pillar, and a second gate insulating layer is provided so as to surround the second Si pillar. A first gate conductor layer connecting to a plate line PL is provided so as to surround the first insulating layer, and a second gate conductor layer connecting to a word line WL is provided so as to surround the second insulating layer. A voltage applied to each of the source line SL, the plate line PL, the word line WL, and the bit line BL is controlled to perform a data write operation for retaining holes, which have been generated through an impact ionization phenomenon or using a gate induced drain leakage current, in a channel region, and a data erase operation for removing the holes from the channel region.