Vertical DRAM Switching Insulating Layer for Leakage Suppression

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing semiconductor devices with vertical channel transistors suffer from leakage current during data storage, leading to short retention time and high power consumption.

Innovation Solution

A semiconductor device is designed with a vertical channel transistor that includes a substrate, bit lines, word lines, channel patterns extending vertically, a gate insulating pattern, switching insulating layers with a thickness allowing electron penetration, and control electrodes to connect the switching insulating layers, thereby suppressing leakage current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If a vertical channel transistor with direct contact between vertical pillar and cell capacitor is used, then the area occupied by each unit cell is reduced, but leakage current flows during data storage causing short retention time

Engineering Contradiction:
Improveunit cell areaVSAvoidretention time
Core Design Contradiction:
Area of stationary objectVSDuration of action of stationary object

Solution Approach 1:

The patent introduces a switching insulating layer as an intermediary component between the vertical channel transistor and the cell capacitor. This switching insulating layer acts as a mediator that blocks leakage current during data storage while allowing electron penetration during write operations, thereby resolving the contradiction between reduced unit cell area and extended retention time

Inventive Principle:
Principle #24Intermediary (Mediator)

2Area of stationary object

If a vertical channel transistor with direct contact between vertical pillar and cell capacitor is used, then the area occupied by each unit cell is reduced, but power consumption increases due to frequent data refresh operations

Engineering Contradiction:
Improveunit cell areaVSAvoidpower consumption
Core Design Contradiction:
Area of stationary objectVSUse of energy by stationary object

Solution Approach 1:

The switching insulating layer serves as a mediator that eliminates the need for frequent data refresh operations by blocking leakage current during storage. This reduces power consumption while maintaining the compact unit cell structure

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the electrical parameter (insulation property) of the switching insulating layer based on operational state - allowing electron penetration during write operations and blocking during read/storage operations. This dynamic parameter change enables leakage suppression without requiring frequent refresh cycles, thereby reducing power consumption

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The semiconductor device effectively suppresses leakage current generation, extends retention time, improves data retention characteristics, and reduces power consumption.

Implementation Method 1

switching insulating layers 60 each formed on upper surfaces of the plurality of channel patterns 40, at least a portion of which has a thickness that an electron can penetrate upon application of a voltage

Methodology Applied
Scientific EffectElectron penetration through insulating layer: Dielectric

Data Source

PatentUS20250133765A1Dram device comprising switching insulating layer
Publication Date: 2025.04.24 TAE SUNG ENVIRONMENT INST CORP
  • US20250133765A1 patent drawing
  • US20250133765A1 patent drawing
  • US20250133765A1 patent drawing

AI summary

A semiconductor device, comprising: a substrate; a plurality of bit lines located on the substrate, and disposed parallel to each other in a first horizontal direction; a plurality of word lines located on the bit line, and disposed parallel to each other in a second horizontal direction substantially perpendicular to the first horizontal direction; a plurality of channel patterns arranged in an array on the bit line, the plurality of channel patterns; a gate insulating pattern located between the plurality of channel patterns and the plurality of word lines; a plurality of switching insulating layers each formed on an upper surface of each of the plurality of channel patterns, at least a portion of which has a thickness that an electron can penetrate upon application of a voltage; and a plurality of control electrodes disposed parallel to each other to connect the plurality of switching insulating layers, is disclosed.