Vertical DRAM Structure with Air Gaps to Reduce Parasitic Capacitance
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Solution Overview
Problem
As semiconductor devices continue to reduce minimum feature sizes for higher integration density, vertical DRAM technology faces challenges in maintaining electrical characteristics and preventing unwanted memory characteristics due to compact layouts, requiring improved separation between memory cells and reduced parasitic capacitance.
Innovation Solution
A vertical DRAM design utilizing a three-dimensional layout with a vertical gate-all-around transistor and capacitor, incorporating a double layer of bit line wirings and air gaps between adjacent word lines to enhance separation and reduce parasitic capacitance, while using monolithic processes for component deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If vertical DRAM structure is implemented to reduce footprint, then memory density is improved, but parasitic capacitance between adjacent memory cells increases
Solution Approach 1:
The bit line wiring is divided into two separate layers (first bit line wiring and second bit line wiring) positioned at different heights. This segmentation separates the electrical pathways vertically, reducing parasitic capacitance coupling between adjacent memory cells while maintaining compact lateral footprint.
Solution Approach 2:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked architecture with bit line wirings arranged in multiple vertical layers. This dimensional change allows memory cells to be packed more densely in the lateral plane while managing parasitic capacitance through vertical separation of conductive elements.
2Quantity of substance
If minimum feature size is reduced to increase integration density, then more components fit in given area, but maintaining electrical characteristics becomes more difficult
Solution Approach 1:
The gate electrode is segmented into multiple portions (first gate electrode portion and second gate electrode portion) that are electrically connected but physically separated. This allows the gate to wrap around multiple channel regions independently, maintaining electrical control effectiveness even as feature sizes are reduced and layout compactness increases.
Solution Approach 2:
The gate dielectric and gate electrode are configured to laterally wrap around the channel region in a nested arrangement, with the gate structure encompassing the channel from multiple sides. This nested configuration ensures effective electrical control and isolation even in compact vertical DRAM layouts with reduced feature sizes.
3Area of stationary object
If compact layout is used to achieve vertical DRAM, then footprint is reduced, but unwanted memory characteristics arise due to proximity of cells
Solution Approach 1:
Dielectric layers are positioned as intermediary structures between adjacent memory cells and between conductive elements. These intermediate dielectric layers provide electrical isolation and prevent unwanted capacitive coupling, allowing compact cell layouts while maintaining distinct electrical characteristics for each memory cell.
Solution Approach 2:
The bit line wiring is segmented into multiple vertically stacked layers, with each layer providing separate electrical pathways. This segmentation prevents parasitic capacitance between adjacent cells by ensuring that bit lines for different cells are electrically isolated through vertical separation, even though the cells are positioned close together in the lateral plane.
Data Source
AI summary
Embodiments provide an integrated capacitor disposed directly over and aligned to a vertical gate all around memory cell transistor. In some embodiments, an air gap may be provided between adjacent word lines to provide a low k dielectric effect between word lines. In some embodiments, a bottom bitline structure may be split across multiple layers. In some embodiments, a second tier of vertical cells may be positioned over a first tier of vertical cells.