Vertical Side-Channel DRAM Structure for Reduced Word Line Coupling
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Solution Overview
Problem
As semiconductor devices, particularly DRAM cells, become more compact to increase integration density, issues such as write line coupling and body effect arise, affecting electrical performance and voltage threshold stability.
Innovation Solution
A vertical DRAM design with side-channel transistors is implemented, which includes a ground gate structure between adjacent memory cells to reduce or eliminate body effect and word line coupling, while allowing for good size scalability without affecting capacitor restore time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional planar DRAM design is used, then manufacturing is simpler, but integration density is limited
Solution Approach 1:
The patent transitions from planar 2D transistor layout to vertical 3D structure by forming channels that extend vertically through the substrate depth. The gate electrode wraps around the channel in a cylindrical configuration, utilizing the third dimension (depth) to achieve higher integration density while maintaining manufacturability through standard semiconductor processing techniques adapted for vertical structures.
2Quantity of substance
If minimum feature size is reduced to increase integration density, then more components fit in given area, but write line coupling and body effect increase
Solution Approach 1:
By moving to vertical channels extending through the substrate, the patent increases spacing between adjacent memory cells in the lateral plane. This vertical configuration reduces capacitive coupling between word lines and minimizes body effect by increasing the distance between neighboring transistor bodies, thereby mitigating harmful interactions while achieving higher density through depth utilization.
Solution Approach 2:
The gate electrode structure acts as an intermediary that wraps around the channel, providing electrical isolation and control. This configuration reduces the impact of write line coupling by distributing the electric field more evenly and minimizing direct capacitive coupling between adjacent cell access lines, thereby reducing harmful effects without sacrificing integration density.
3Object-affected harmful factors
If vertical DRAM design with side-channel transistors is implemented, then body effect and word line coupling are reduced, but device structure becomes more complex
Solution Approach 1:
The gate electrode structure serves multiple functions simultaneously: it controls the vertical channel conduction, provides electrical isolation to reduce body effect, and acts as a shielding structure to minimize word line coupling. By combining these functions into a single wrapped electrode structure, the patent reduces harmful effects without proportionally increasing device complexity.
Solution Approach 2:
The patent merges the control gate function with the isolation and shielding functions into a single integrated gate electrode structure. This combined structure wraps around the channel and simultaneously achieves transistor control, body effect reduction, and word line coupling mitigation, thereby reducing harmful effects while keeping the added structural complexity manageable through functional integration.
Data Source
AI summary
Embodiments of the present disclosure provide a side-channel dynamic random access memory (DRAM) cell and cell array that utilizes a vertical design with side channel transistors. A dielectric layer disposed over a substrate. A gate electrode is embedded in the dielectric layer. A channel layer wraps the gate electrode and a conductive structure is adjacent to the channel layer, with the channel layer interposed between the gate electrode and the conductive structure. The semiconductor structure also includes a dielectric structure disposed over the conductive structure and the gate electrode, the channel layer extending up through the dielectric structure.