Vertical Dual-Channel TFT Array for Smaller Transistor Footprints
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Solution Overview
Problem
The manufacturing process of electronic devices, particularly display devices, is complicated due to the need for numerous transistors, which complicates panel production and can degrade device performance, and it is technically difficult to reduce transistor area without degrading characteristics.
Innovation Solution
A thin film transistor array substrate with a vertical-structure transistor design that includes a first and second channel area on the side surface of an insulation film, allowing for a short channel, reduced area, and enhanced current characteristics, along with improved processing convenience.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If numerous transistors are disposed to drive the panel, then the device functionality is improved, but the manufacturing process becomes complicated and device performance degrades
Solution Approach 1:
The patent merges the source electrode and drain electrode functions into a single first electrode structure, while the active layer forms two distinct channel areas (first and second channel areas) that function as separate transistor channels. This integration reduces the number of discrete electrode components needed while maintaining dual-transistor functionality, thereby simplifying the manufacturing process without compromising device capability.
Solution Approach 2:
The first electrode serves multiple functions: it acts as both the source electrode for the first transistor and the drain electrode for the second transistor. Similarly, the active layer structure provides dual channel functionality. This multi-functionality reduces the total component count and simplifies the overall device architecture, addressing the contradiction between functionality and manufacturing complexity.
2Productivity
If transistor area is reduced to increase integration, then productivity is improved, but it is technically difficult to maintain transistor characteristics
Solution Approach 1:
The patent transitions from a conventional planar transistor structure to a vertical-channel structure where the channel extends in the thickness direction of the layers. The active layer contacts the first electrode at its bottom surface and extends upward, creating vertical channel areas. This dimensional change allows for shorter channel lengths without proportionally reducing the channel width, enabling area reduction while maintaining current characteristics.
Solution Approach 2:
The invention changes the geometric parameters of the transistor structure by forming vertical channels with controlled heights and widths. The channel length is defined by the vertical extent of the active layer, while the channel width is determined by the horizontal dimensions. By optimizing these parameters, the patent achieves miniaturization while preserving adequate current flow characteristics.
3Ease of manufacture
If conventional planar transistor structure is used, then processing is simple, but area occupation is large and current characteristics are limited
Solution Approach 1:
The patent employs a vertical-channel structure where the channel extends perpendicular to the substrate plane, utilizing the thickness direction of the layered structure. This vertical arrangement allows the channel length to be independent of the planar footprint, enabling compact transistor designs that occupy less area while maintaining adequate channel dimensions for good current characteristics.
Solution Approach 2:
The active layer is positioned within and contacts the first electrode structure, with the gate electrode overlapping the active layer in the vertical stacking sequence. This nested arrangement maximizes the use of vertical space, allowing the channel to extend through multiple layers without increasing the planar area occupation, thereby achieving miniaturization.
4Area of stationary object
If transistor area is reduced, then area occupation is improved, but processing convenience may be degraded
Solution Approach 1:
The active layer is segmented into distinct regions: a first channel area and a second channel area, separated by a third area. This segmentation allows for precise control of the channel geometry and facilitates the formation of the vertical structure through controlled deposition and etching processes. The segmented structure can be formed using standard semiconductor fabrication techniques, maintaining processing convenience.
Solution Approach 2:
By forming the channel in the vertical dimension rather than extending it laterally, the patent reduces the planar footprint without requiring proportionally smaller feature sizes. The vertical channel height can be controlled by thin-film deposition thickness, which is a precise and convenient parameter to control in semiconductor manufacturing, thus maintaining ease of fabrication.
Data Source
AI summary
A thin film transistor array substrate includes a first electrode, a first insulation film including a hole exposing a portion of an upper surface of the first electrode, an active layer contacting a portion of an upper surface of the first insulation film and the portion of the upper surface of the first electrode, a second insulation film disposed on the active layer, a gate electrode disposed on the second insulation film, a third insulation film disposed on the gate electrode, and a second electrode and a third electrode disposed on the third insulation film, and electrically connected with the active layer, wherein the active layer includes a first channel area and a second channel area spaced apart from each other, and wherein the first channel area and the second channel area include an area positioned on a side surface of the hole of the first insulation film.