Vertical Dual-Gate DRAM Gate Control via Dielectric Spacers
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Solution Overview
Problem
Conventional methods for fabricating gates in transistors at smaller feature sizes face challenges in controlling gate thickness and separation, leading to difficulties in reducing chip dimensions and increasing production costs.
Innovation Solution
A method for controlling a vertical dual-gate DRAM that eliminates the need for etching by using a dielectric layer to space gates from pillars, allowing for control of electric connections between source and drain via multiple gates without cutting or separating the gates, thereby avoiding the etching process and preventing current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If etching process is used to form gates on two sides of pillar, then transistor functionality is achieved, but manufacturing precision deteriorates due to difficulty in controlling gate thickness at smaller feature sizes
Solution Approach 1:
The patent introduces a dielectric layer as an intermediary substance between the metal gate and the pillar. This dielectric layer serves as a spacer that precisely defines the gate position and thickness without requiring etching of the gate material itself. The gate thickness is controlled by the thickness of the deposited dielectric layer, which can be precisely controlled by CVD or PVD processes, thereby resolving the thickness control issue at small feature sizes.
Solution Approach 2:
The dielectric layer is deposited on the pillar surface before the metal gate is formed. This preliminary deposition of the dielectric spacer establishes the gate dimensions and position in advance, eliminating the need for subsequent etching steps to define the gate thickness. The gate is then formed conformally on top of this pre-defined dielectric layer.
2Ease of manufacture
If etching process is used to separate gates in trenches, then gate isolation is achieved, but device complexity increases due to difficulty in separating gates at smaller feature sizes
Solution Approach 1:
The dielectric layer acts as a physical intermediary that separates adjacent gates. Instead of using etching to create gaps between gates, the patent uses deposited dielectric material to fill the spaces between pillars and gates, providing natural isolation. This eliminates the complex etching steps required to separate gates while maintaining proper electrical isolation.
3Ease of manufacture
If conventional single-gate structure is used, then manufacturing is simpler, but data reading accuracy deteriorates due to current leakage during state transitions
Solution Approach 1:
The patent divides the gate control into two separate gates (first gate and second gate) that can be independently controlled. This segmentation allows one gate to be turned off while the other remains on, enabling precise control of current flow paths. During state transitions, this dual-gate structure prevents unwanted current leakage by ensuring proper isolation, thereby improving data reading accuracy.
Solution Approach 2:
The patent implements dynamic control of the dual gates with different timing. The first gate and second gate are switched at different times during read/write operations, allowing flexible control of the transistor state transitions. This dynamic gating scheme enables precise control of current flow and prevents leakage during transitions, improving reliability while maintaining manufacturing simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the fabrication of transistors at smaller feature sizes without the etching process, improving data reading accuracy and reducing production costs by controlling gate voltages to manage electric connections and prevent current leakage.
Implementation Method 1
a dielectric layer formed on the surface of the trench... spaced from the pillars by the dielectric layer
Implementation Method 2
control a first gate and a second gate which are located at two sides of the first pillar to respectively have a turn-on voltage to form electric connection between a drain and a source
Data Source
AI summary
A method of controlling a vertical dual-gate DRAM provides a short circuit state, a clearing state and a false broken circuit state. In the short circuit state, a first gate and a second gate at two sides of a first pillar are controlled to respectively have a turn-on voltage to form electric connection between a drain and a source at two ends of the first pillar. In the clearing state, the first gate and second gate are controlled to respectively have a clearing voltage to disconnect electric connection between the drain and source at two ends of the first pillar. The false broken circuit state is entered after the clearing state has been finished. The invention does not separate gates between neighboring pillars, but controls ON/OFF of transistors electrically so that no current leakage is generated in the clearing state and problem of inaccurate data reading can be prevented.