Vertical eFuse Memory Cell Layout for Higher Chip Density
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Solution Overview
Problem
The challenge is to reduce the area occupied by eFuse memory cells in integrated circuits (ICs) as the size reduction of eFuse memory devices has not kept pace with the advancement of IC features, leading to a need for a more compact eFuse memory cell structure.
Innovation Solution
The eFuse memory cell structure is redesigned with access transistors formed over the eFuse resistor in a metallization layer, connected through metallization layers and via structures, and peripheral circuits such as power switches and header circuits are positioned above the eFuse resistors and control circuits, allowing for a reduction in cell area and increased memory chip density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If eFuse memory cells are designed with traditional lateral configuration, then the device structure is simple and easy to manufacture, but the cell area is large and does not scale with IC feature size reduction
Solution Approach 1:
The patent transitions from a traditional lateral configuration to a vertical stacking architecture where the access transistor is positioned above the eFuse resistor in different metallization layers. This dimensional change from 2D lateral layout to 3D vertical stacking dramatically reduces the cell area while maintaining the 1T1R functional configuration, enabling scaling with advanced IC technologies.
Solution Approach 2:
The patent implements a nested structure where the access transistor is formed over the eFuse resistor, with control circuits positioned below and peripheral circuits positioned above the eFuse resistors. This nested arrangement allows multiple functional blocks to occupy overlapping spatial footprints, maximizing space utilization and reducing overall cell area.
2Productivity
If access transistors are formed over eFuse resistors in metallization layers, then memory chip density increases, but fabrication process complexity increases
Solution Approach 1:
The patent divides the eFuse memory cell into distinct functional layers: the eFuse resistor in lower metallization layers, the access transistor in upper metallization layers, control circuits below the resistors, and peripheral circuits above the resistors. This segmentation allows each component to be optimized and fabricated independently using standard CMOS processes, making the complex 3D structure manufacturable with existing technology.
Solution Approach 2:
The patent utilizes standard CMOS fabrication processes and existing metallization layers to implement the vertical stacking architecture. The same fabrication techniques used for conventional planar devices are adapted for the vertical configuration, allowing the complex structure to be manufactured using universal, existing manufacturing capabilities without requiring entirely new process equipment.
3Area of moving object
If peripheral circuits are positioned above eFuse resistors, then cell area is reduced, but device complexity increases
Solution Approach 1:
The patent merges the peripheral circuits (power switches and header circuits) with the eFuse array structure by positioning them above the eFuse resistors in the same vertical space. This merging allows peripheral functions to be integrated within the memory array footprint rather than occupying separate lateral space, reducing overall cell area while consolidating multiple functions into a unified 3D structure.
Data Source
AI summary
A memory device is disclosed. The memory device includes a plurality of memory cells, each of the memory cells including an access transistor and a resistor coupled to each other in series. The resistors of the memory cells are each formed as one of a plurality of interconnect structures disposed over a substrate. The access transistors of the memory cells are disposed opposite a first metallization layer containing the plurality of interconnect structures from the substrate.