Multilayer Ceramic Capacitor with Vertical Electrodes for Low Inductance
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Solution Overview
Problem
Existing decoupling capacitors face challenges in reducing inductance, leading to unacceptable voltage spikes in high-speed electronic circuits, as conventional designs fail to minimize the current loop area and equivalent series inductance (ESL) effectively.
Innovation Solution
The design incorporates vertically oriented electrodes and closely spaced termination gaps to minimize the current loop area, achieved through specific electrode configurations and termination layer arrangements, allowing for direct soldering to circuit board pads without the need for solder balls, thereby reducing ESL and equivalent series resistance (ESR).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If conventional capacitor designs are used, then manufacturing is simpler, but inductance and voltage spikes become unacceptable in high-speed circuits
Solution Approach 1:
The capacitor is divided into multiple electrode layers (first electrode layers and second electrode layers) with alternating polarity, where each layer is segmented into multiple regions. This segmentation allows current to flow through multiple parallel paths, reducing the overall current loop area and inductance, thereby minimizing voltage spikes in high-speed circuits.
Solution Approach 2:
The patent transitions from conventional planar electrode arrangements to a three-dimensional stacked configuration with vertically oriented electrodes extending through multiple dielectric layers. This dimensional change creates closely spaced termination gaps and minimizes the current loop area, significantly reducing inductance and voltage spikes.
2Object-affected harmful factors
If inductance is reduced through conventional methods, then voltage spikes decrease, but equivalent series resistance remains high
Solution Approach 1:
The patent combines multiple electrode layers and termination layers into an integrated structure where first and second conductive termination layers are merged with the electrode ends. This merging creates direct electrical connections with minimal intermediate elements, reducing equivalent series resistance while maintaining low inductance, thereby improving high-frequency performance.
Solution Approach 2:
The termination layers are pre-configured and positioned closely spaced to the electrode ends before final assembly, establishing optimal current paths in advance. This preliminary arrangement minimizes the formation of large current loops and reduces both inductance and equivalent series resistance, enhancing high-frequency performance.
3Object-affected harmful factors
If vertically oriented electrodes with closely spaced termination gaps are used, then current loop area is minimized, but manufacturing precision requirements increase
Solution Approach 1:
The electrode structure is segmented into multiple discrete layers with standardized dimensions, allowing the termination gaps to be consistently formed through repetitive manufacturing processes. This segmentation enables precise control of gap spacing through modular design, minimizing current loop area while managing manufacturing precision requirements.
Solution Approach 2:
The patent optimizes the spacing parameter of termination gaps to specific dimensional ranges that balance current loop area minimization with manufacturing feasibility. By carefully selecting and controlling the gap distance parameter, the design achieves low inductance without requiring excessive manufacturing precision, thereby minimizing voltage spikes while remaining manufacturable.
Data Source
AI summary
Low inductance capacitors include electrodes that are arranged among dielectric layers and oriented such that the electrodes are substantially perpendicular to a mounting surface. Vertical electrodes are exposed along a device periphery to determine where termination lands are formed, defining a narrow and controlled spacing between the lands that is intended to reduce the current loop area, thus reducing the component inductance. Further reduction in current loop area and thus component equivalent series inductance (ESL) may be provided by interdigitated terminations. Terminations may be formed by various electroless plating techniques, and may be directly soldered to circuit board pads. Terminations may also be located on “ends” of the capacitors to enable electrical testing or to control solder fillet size and shape. Two-terminal devices may be formed as well as devices with multiple terminations on a given bottom (mounting) surface of the device. Terminations may also be formed on the top surface (opposite a designated mounting surface) and may be a mirror image, reverse-mirror image, or different shape relative to the bottom surface.