Vertical Emitter Modules With Integrated III-V Transistor Switching
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Solution Overview
Problem
Conventional optoelectronic devices face challenges in integrating high-power vertical emitters with control circuits due to the need for large final-stage transistors in silicon control circuits, which exceed conventional CMOS operating ranges, leading to increased size, voltage, and power requirements.
Innovation Solution
Integrate a transistor in series with the vertical emitter within the III-V epitaxial stack, utilizing heterojunction bipolar transistors (HBTs) or bipolar junction transistors (BJTs) to actuate the emitters, reducing the need for large transistors in silicon control circuits and enabling operation at lower voltage and power levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If large final-stage transistors are used in silicon control circuits to actuate high-power vertical emitters, then the emitters can be driven with sufficient power, but the size, voltage, and power requirements of the control circuits increase significantly
Solution Approach 1:
The patent merges the final-stage transistor with the vertical emitter structure by integrating it within the III-V epitaxial stack. This combination allows the transistor to be formed simultaneously with the emitter components during the same epitaxial growth process, creating a unified structure that reduces overall device complexity while maintaining high-power output capability. The merged structure eliminates the need for separate large transistors in silicon control circuits.
Solution Approach 2:
The patent employs composite materials by integrating the transistor within the III-V epitaxial stack that forms the vertical emitter. This composite structure combines the advantages of III-V semiconductor materials for high-power emission with transistor functionality, allowing the device to operate at lower voltage and power levels while achieving the required output power through the integrated structure.
2Ease of manufacture
If conventional CMOS control circuits are used to drive vertical emitters, then standard fabrication processes can be employed, but the circuits require large transistors that exceed conventional CMOS operating ranges
Solution Approach 1:
The patent changes the operating parameters of the control circuit by integrating the transistor within the III-V epitaxial stack. This integration enables the circuit to operate at lower voltage and power levels, extending the adaptability beyond conventional CMOS operating ranges. The parameter changes are achieved through the physical integration that allows direct coupling and optimized electrical characteristics.
Solution Approach 2:
The use of III-V epitaxial materials for integrating the transistor provides both ease of manufacture through established epitaxial growth processes and enhanced adaptability. The composite material approach allows the device to operate in extended voltage and power ranges while maintaining compatibility with standard semiconductor fabrication techniques.
3Adaptability or versatility
If III-V semiconductor substrates are thinned away from the back side of vertical emitters, then bottom-emitting configuration is achieved, but mechanical support and heat dissipation require additional components
Solution Approach 1:
The patent merges the control circuit substrate with the vertical emitter structure by bonding the III-V epitaxial stack to the silicon control circuit substrate. This integration provides mechanical support for the thinned III-V substrate while enabling bottom-emitting configuration. The combined structure eliminates the need for separate mechanical support components by making the control circuit substrate serve dual purposes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This integration reduces the size, voltage, and power requirements of the control circuits, allowing for efficient actuation of high-power optical pulses with sharp rising and falling edges, while obviating the need for large driver capacitors.
Implementation Method 1
upper and lower distributed Bragg reflectors (DBRs) on opposing sides of the optically active layer
Implementation Method 2
a transistor in series with the vertical emitter and including a terminal in contact with a respective one of the control circuits, so as to actuate the vertical emitter in response to a control signal
Implementation Method 3
the transistor includes a bipolar junction transistor (BJT)
Data Source
AI summary
An integrated emitter device incudes a silicon die, including an array of control circuits, and a plurality of integrated emitter modules disposed on the silicon die. Each integrated emitter module includes a single epitaxial stack comprising multiple layers of III-V semiconductor compounds, which define a vertical emitter including an optically active layer and upper and lower distributed Bragg reflectors (DBRs) on opposing sides of the optically active layer, and a transistor in series with the vertical emitter and including a terminal in contact with a respective one of the control circuits, so as to actuate the vertical emitter in response to a control signal applied to the terminal by the respective one of the control circuits.