Vertical ESD Diode Thyristor Structure Leakage Reduction

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Solution Overview

Problem

As semiconductor devices scale down, reducing residual current and dynamic resistance in ESD protection diodes becomes necessary to protect them from electrostatic discharge, while also minimizing chip size and cost.

Innovation Solution

The implementation of a vertical ESD protection diode with a thyristor structure and specific impurity regions and electrodes, along with a wiring layer and insulating layers, allows for reduced dynamic resistance and chip cost by expanding the current path within the semiconductor layer and using a mold package, and the inclusion of barrier regions to suppress leakage current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If the device to be protected is scaled down, then chip size is reduced, but residual current flowing into the device increases

Engineering Contradiction:
Improvechip sizeVSAvoidresidual current
Core Design Contradiction:
Volume of moving objectVSObject-generated harmful factors

Solution Approach 1:

The patent applies local quality by creating specific impurity concentration distributions in different regions of the semiconductor layer. The first and second impurity regions have different conductivity types and concentration levels, allowing localized control of electrical properties to reduce residual current while maintaining small chip size.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes physical parameters by adjusting impurity concentration levels and conductivity types in different regions. By modifying the electrical parameters (impurity concentration, conductivity) locally, the patent achieves reduced residual current without increasing chip dimensions.

Inventive Principle:
Principle #35Parameter changes

2Object-generated harmful factors

If the clamp voltage and dynamic resistance of the ESD protection diode are reduced, then residual current is reduced, but device complexity increases

Engineering Contradiction:
Improveresidual currentVSAvoiddevice structure
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The patent merges multiple functions into a single ESD protection diode structure. The first and second impurity regions are integrated within the same semiconductor layer to simultaneously achieve low clamp voltage and low dynamic resistance, reducing the need for additional protective components.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The ESD protection diode structure performs multiple protective functions through its multi-region impurity structure. The different impurity regions work together to provide both voltage clamping and current diversion capabilities, making the single device universally effective against various ESD scenarios.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Object-generated harmful factors

If a vertical ESD protection diode with thyristor structure is implemented, then dynamic resistance is reduced, but manufacturing complexity increases

Engineering Contradiction:
Improvedynamic resistanceVSAvoidmanufacturing process
Core Design Contradiction:
Object-generated harmful factorsVSEase of manufacture

Solution Approach 1:

The patent transitions from a lateral device structure to a vertical structure by extending the impurity regions through the thickness of the semiconductor layer. This dimensional change enables the thyristor structure to achieve low dynamic resistance while maintaining compatibility with standard vertical semiconductor manufacturing processes.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS10896903B2Semiconductor device
Publication Date: 2021.01.19 KK TOSHIBA
  • US10896903B2 patent drawing
  • US10896903B2 patent drawing
  • US10896903B2 patent drawing

AI summary

A semiconductor device according to an embodiment includes a semiconductor layer having first and second plane, a first conductivity-type first semiconductor region, a second conductivity-type second semiconductor region between the first semiconductor region and the first plane, a first conductivity-type third semiconductor region between the second semiconductor region and the first plane, a second conductivity-type fourth semiconductor region between the third semiconductor region and the first plane, a first conductivity-type fifth semiconductor region provided between the first semiconductor region and the first plane, a first electrode provided on a side of the first plane, and electrically connected to the third semiconductor region and the fourth semiconductor region, a second electrode provided on a side of the second plane, and electrically connected to the first semiconductor region, and a conductive layer provided on a side of the first plane, and electrically connecting the second and the fifth semiconductor region.