Vertical ESD Protection Structure With Low Parasitic Capacitance
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Solution Overview
Problem
Conventional methods for manufacturing ultrathin silicon wafers face challenges such as silicon split-offs and fissures during dicing, and achieving low intrinsic resistance and capacitance in electrostatic discharge protection devices, especially in chip-scale packages, is difficult and costly.
Innovation Solution
A method involving a semiconductor carrier with vertically integrated electronic structures connected by an electrical connection layer, mounted on a support carrier, and thinned to reduce parasitic resistances and capacitances, using a permanent carrier system to decouple I/O pins and achieve a low resistance connection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional methods are used to manufacture ultrathin silicon wafers, then the wafer thickness can be reduced, but silicon split-offs and fissures occur during dicing
Solution Approach 1:
The patent divides the wafer processing into distinct stages: maintaining full wafer structure during dicing, then selectively removing substrate material in separation regions after dicing is complete. This segmentation allows dicing to occur on structurally sound wafers while achieving separation later, avoiding split-offs and fissures.
Solution Approach 2:
The patent performs dicing on complete wafers before substrate removal, establishing the preliminary structure integrity needed for reliable dicing. The separation regions are then removed as a subsequent action, ensuring that the critical dicing operation occurs when the wafer has maximum structural support.
2Device complexity
If vertically integrated electronic structures are used in chip-scale packages, then device integration is improved, but achieving low intrinsic resistance and capacitance becomes difficult and costly
Solution Approach 1:
The patent extracts and removes the substrate material in separation regions between vertically integrated structures, eliminating the parasitic resistance and capacitance that would otherwise be introduced by the substrate. This extraction achieves low intrinsic resistance and capacitance without requiring complex alternative structures.
Solution Approach 2:
The patent applies different treatments to different regions: vertically integrated structures are maintained with full substrate support for mechanical strength, while separation regions between structures have substrate removed to minimize parasitic effects. This local differentiation achieves low resistance/capacitance where needed while maintaining structural integrity where required.
3Reliability
If substrate material is removed to reduce parasitic resistance and capacitance, then electrical performance is improved, but mechanical stability during manufacturing deteriorates
Solution Approach 1:
The patent segments the substrate removal operation to occur only in separation regions between devices, not under the devices themselves. This selective segmentation maintains mechanical stability during manufacturing while achieving the electrical performance benefits of reduced parasitic resistance and capacitance in the critical separation areas.
Solution Approach 2:
The patent performs all dicing and initial structuring operations while the substrate is still intact and providing mechanical support. Only after these manufacturing steps are complete does the patent remove substrate material in separation regions, ensuring mechanical stability is maintained during the most critical manufacturing operations.
Data Source
AI summary
An ESD protection device may include: a first vertically integrated ESD protection structure comprising a first semiconductor portion, a first contact region disposed on a first side of the first semiconductor portion and a first terminal exposed on a second side of the first semiconductor portion opposite the first side of the first semiconductor portion, a second vertically integrated ESD protection structure comprising a second semiconductor portion, a second contact region disposed on a first side of the second semiconductor portion and a second terminal exposed on a second side of the second semiconductor portion opposite the first side of the second semiconductor portion, an electrical connection layer, wherein the first vertically integrated ESD protection structure and the second vertically integrated ESD protection structure are disposed on the electrical connection layer laterally separated from each other and are electrically connected with each other anti-serially via the electrical connection layer.