Vertical ESD Protection Layout for Stacked-Channel IGFETs
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Solution Overview
Problem
As transistor sizes shrink, electrostatic discharge (ESD) becomes more problematic due to smaller gate dielectric thicknesses and shorter transistor channels, and existing ESD protection circuit structures often conflict with new technology or occupy too much active footprint in integrated circuit devices.
Innovation Solution
The integration of ESD protection circuit structures with vertically stacked channels and improved gate control, where the ESD protection circuit is formed in a layer below the input/output circuit, reducing footprint and current leakage while maintaining reliable ESD protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional ESD protection circuit structures are used, then ESD protection capability is provided, but the footprint area is too large and conflicts with new technology node requirements
Solution Approach 1:
The patent transitions from planar ESD protection structures to vertically stacked three-dimensional structures. The ESD protection circuit is formed in a layer below the input/output circuit, utilizing the vertical dimension to reduce the horizontal footprint area while maintaining ESD protection functionality through multiple stacked channels
Solution Approach 2:
The ESD protection circuit is nested within the vertical stack beneath the main input/output circuit. The vertically stacked channels are positioned in layers below the primary circuit layer, allowing the ESD protection structure to be contained within the vertical profile rather than expanding horizontally
2Productivity
If transistor sizes are reduced to achieve higher integration, then device density increases, but ESD protection becomes more problematic due to smaller gate dielectric thicknesses and shorter channels
Solution Approach 1:
The patent addresses the ESD vulnerability of scaled transistors by moving the ESD protection structure to the vertical dimension. The stacked channels extend vertically below the main circuit layer, providing adequate channel length for ESD protection without consuming horizontal space that would reduce device density
Solution Approach 2:
The ESD protection circuit is segmented into multiple vertically stacked channels rather than using a single planar structure. This segmentation allows each channel to maintain sufficient length for ESD protection while the vertical stacking arrangement preserves horizontal space for high device density
Data Source
AI summary
An integrated circuit device having insulated gate field effect transistors (IGFETs) having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure has been disclosed. The integrated circuit device may include electrostatic discharge (ESD) protection circuit structures. The ESD protection circuit structures may be formed in regions other than the region that the IGFETs are formed as well as in the region that the IGFETs having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure are formed. By forming ESD protection circuit structures in regions below the IGFETs, an older process technology may be used and device size may be decreased. Furthermore, planar IGFETs of FinFETs may be formed in other regions to decrease device size and improve costs.