Vertical Extension Regions for Lateral Scaling in Semiconductor Devices
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Solution Overview
Problem
Current methods for scaling semiconductor devices, such as MOSFETs and CMOS, face challenges in achieving higher integration density and improved performance due to limitations in downsizing field effect transistors while maintaining electrical properties.
Innovation Solution
The method involves forming raised extension regions and source/drain regions on a semiconductor substrate using epitaxial growth and in-situ doping, which allows for precise control of dopant concentration and vertical extension length, avoiding the uncontrolled lateral diffusion associated with ion implantation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional scaling methods are used to downsize field effect transistors, then device dimensions are reduced, but uncontrolled lateral diffusion of dopants occurs leading to poor manufacturing precision
Solution Approach 1:
The patent transitions from planar (2D) doping to vertical (3D) doping by forming raised extension regions that extend upward from the substrate surface. This vertical dimension allows dopants to be confined in the vertical direction while preventing lateral diffusion, thereby achieving precise dopant concentration control during device scaling.
Solution Approach 2:
The patent changes the physical state and spatial configuration of dopant regions by forming raised extension regions with controlled height and dopant concentration profiles. By adjusting the vertical extension length and dopant concentration parameters, precise control over dopant distribution is achieved without the lateral diffusion problems of conventional planar doping.
2Productivity
If device dimensions are scaled down to achieve higher integration density, then compactness is improved, but maintaining electrical properties becomes difficult
Solution Approach 1:
The patent applies different dopant concentrations and vertical extension lengths to different regions of the device. The raised extension regions have higher dopant concentrations than the substrate, creating locally optimized electrical properties in critical areas while maintaining overall device scaling for high integration density.
3Quantity of substance
If ion implantation is used for doping, then dopant introduction is achieved, but uncontrolled lateral diffusion occurs reducing manufacturing precision
Solution Approach 1:
The patent replaces conventional planar ion implantation with vertical ion implantation into raised extension regions. This vertical approach confines dopant diffusion to the vertical direction where it can be controlled by the region's height, preventing the uncontrolled lateral diffusion that plagues traditional doping methods.
Solution Approach 2:
The raised extension regions act as intermediary structures that mediate between the ion implantation process and the final dopant distribution. These vertical structures serve as templates that guide and confine dopant atoms, ensuring precise spatial control over where dopants are introduced and how they distribute during subsequent thermal processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of semiconductor devices with enhanced performance and integration density by precisely controlling the dopant concentration and extension length, improving the scalability and electrical properties of field effect transistors.
Implementation Method 1
The method involves forming raised extension regions and source/drain regions on a semiconductor substrate using epitaxial growth and in-situ doping
Implementation Method 2
The method involves forming raised extension regions and source/drain regions on a semiconductor substrate using epitaxial growth and in-situ doping, which allows for precise control of dopant concentration
Data Source
AI summary
A method of forming a semiconductor device is provided, in which extension regions are formed atop the substrate in a vertical orientation. In one embodiment, the method includes providing a semiconductor substrate doped with a first conductivity dopant. Raised extension regions are formed on first portions of the semiconductor substrate that are separated by a second portion of the semiconductor substrate. The raised extension regions have a first concentration of a second conductivity dopant. Raised source regions and raised drain regions are formed on the raised extension regions. The raised source regions and the raised drain regions each have a second concentration of the second conductivity dopant, wherein the second concentration is greater than the first concentration. A gate structure is formed on the second portion of the semiconductor substrate.