Vertical Layered FAID for High-Throughput LDPC Decoding
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Solution Overview
Problem
Conventional LDPC decoders face challenges in achieving low error rates and high throughput while maintaining low hardware costs, with existing approaches often requiring significant resources and power, and previous solutions focused primarily on FAIDs for LDPC codes with fixed column-weight dv=3, which are not sufficient for storage applications.
Innovation Solution
The implementation of vertical layered finite alphabet iterative decoding, which processes messages between variable and check nodes using a parity-check matrix composed of row and column blocks, allowing for flexible hardware architectures and improved error correction capabilities across both fixed and variable column-weight LDPC codes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional LDPC decoders use traditional decoding algorithms, then error correction capability is maintained, but hardware resources and power consumption increase significantly
Solution Approach 1:
The parity-check matrix H is divided into multiple column blocks, where each column block contains multiple sub-matrices. The decoding process is segmented to process one column block at a time, allowing the hardware to focus on smaller, manageable subsets of the full code structure. This segmentation enables reuse of computational resources across different column blocks, reducing overall hardware requirements while maintaining full error correction capability.
Solution Approach 2:
The decoding algorithm employs periodic action by repeatedly processing column blocks in a systematic sequence. The same hardware structure is applied periodically to each column block, with results accumulated across iterations. This periodic processing approach allows limited hardware resources to achieve the functionality of a larger system through repeated application over time.
2Measurement precision
If conventional LDPC decoders process the entire parity-check matrix simultaneously, then decoding accuracy is improved, but throughput is limited and resource usage increases
Solution Approach 1:
The parity-check matrix processing is segmented into column block-level operations. Each column block is processed independently and completely before moving to the next column block. This segmentation enables pipelining and parallel processing of different column blocks, significantly increasing throughput while ensuring that each block receives the full attention needed for accurate decoding.
Solution Approach 2:
The decoding process maintains continuity of useful action by systematically processing column blocks in sequence without idle periods. While one column block is being processed, preparation for the next block can occur simultaneously, ensuring continuous utilization of hardware resources. The iterative nature of the algorithm ensures that decoding accuracy improves with each complete pass through all column blocks.
3Device complexity
If previous FAID solutions are used for LDPC codes with fixed column-weight dv=3, then implementation is simplified, but error correction performance is insufficient for storage applications
Solution Approach 1:
The decoding algorithm is designed with universality to handle both fixed column-weight (dv=3) and variable column-weight LDPC codes using the same hardware structure and processing logic. The column block processing approach and sub-matrix operations remain consistent regardless of the specific code parameters, allowing a single implementation to serve multiple code types and applications, including storage systems requiring higher error correction performance.
Data Source
AI summary
This invention presents a method and apparatus for vertical layered finite alphabet iterative decoding of low-density parity-check codes (LDPC) which operate on parity check matrices that consist of blocks of sub-matrices. The iterative decoding involves passing messages between variable nodes and check nodes of the Tanner graph that associated with one or more sub-matrices constitute decoding blocks, and the messages belong to a finite alphabet. Various embodiments for the method and apparatus of the invention are presented that can achieve very high throughputs with low hardware resource usage and power.