Vertical Ferroelectric Transistor for High Density Memory
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Solution Overview
Problem
Conventional horizontal ferroelectric thin film storage transistors occupy significant chip area due to parallel channel configuration, limiting the density of memory cells that can be formed in a limited chip area.
Innovation Solution
A vertical ferroelectric thin film storage transistor is developed with a substrate, conductive structures, insulating layers, a channel layer, inner dielectric layer, ferroelectric layer, and gate structure, where the channel flows perpendicular to the substrate surface, allowing for a more compact design and increased memory cell density by reducing chip area occupancy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a horizontal ferroelectric thin film storage transistor is used with parallel channel configuration, then the contact surface area between source/drain and conductive structures is sufficient, but the chip area occupied is large, limiting memory cell density
Solution Approach 1:
The patent transitions from a horizontal planar configuration to a vertical three-dimensional configuration. The channel is formed vertically along the sidewall of a hole structure, with the gate wrapping around the ferroelectric layer in a cylindrical manner. This dimensional change allows the transistor to occupy significantly less chip area while maintaining sufficient contact surfaces through the vertical stacking of source, drain, and gate structures.
2Reliability
If the contact surfaces and gate are enlarged to lower circuit resistance, then the electrical performance is improved, but the chip area occupied increases, reducing the number of memory cells that can be formed
Solution Approach 1:
The vertical configuration allows the gate to wrap around the ferroelectric layer in a cylindrical manner, increasing the effective gate-contact surface area and improving electrical contact without expanding the horizontal footprint. The source and drain contacts are positioned at the top and bottom of the vertical structure, providing sufficient contact area for low resistance while maintaining a compact chip area occupation.
Solution Approach 2:
The gate structure is nested around the ferroelectric layer in a cylindrical configuration, with the channel layer forming on the sidewall of the hole. This nested arrangement maximizes the contact surface area between gate and channel within a compact volume, improving electrical performance without increasing chip area.
3Ease of manufacture
If a conventional horizontal ferroelectric thin film storage transistor is used, then the manufacturing process is straightforward, but the memory cell density is limited due to large area occupation
Solution Approach 1:
The patent employs vertical hole formation through the substrate using standard photolithography and etching techniques, followed by atomic layer deposition (ALD) for forming the channel, dielectric, and ferroelectric layers on the hole sidewalls. The gate is formed by depositing conductive material and patterning it in a cylindrical configuration. These processes build upon conventional semiconductor manufacturing techniques while achieving higher density through vertical stacking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The vertical configuration significantly reduces chip area usage, enabling the formation of more memory cells in the same area, thereby improving the efficiency and density of memory cell placement compared to traditional horizontal designs.
Implementation Method 1
a ferroelectric layer 14, a source 16 and a drain 18. Under certain voltage conditions, a semiconductor channel 19 is formed between the source 16 and the drain 18
Data Source
AI summary
A vertical ferroelectric thin film storage transistor and a data write and read method thereof are disclosed. The vertical ferroelectric thin film storage transistor includes a substrate having a first surface, a first conductive structure, a first insulating layer, a second conductive structure, and a second insulating layer sequentially disposed above a first surface of a substrate, and a vertical hole penetrates through the layers in a direction substantially perpendicular to the first surface of the substrate. A channel layer is disposed on a wall surface of the vertical hole and in electrical contact with the first conductive structure and the second conductive structure. An inner dielectric layer is disposed on one side of the channel layer. A ferroelectric layer is disposed on one side of the inner dielectric layer. A gate structure is disposed on one side of the ferroelectric layer. A third conductive structure is disposed above the second insulating layer or in the substrate, and in electrical contact with the third conducting structure and the gate structure.